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Phase relationships for External PLL signals with the LVDS SERDES Receiver IP core



I am using the LVDS SERDES Receiver IP core on a Cyclone V. I'm using an external PLL and am trying to understand how to adjust the phase relationships for clock and data inputs that are not edge aligned. I am confused by Figure 9. of the LVDS SERDES IP Core User guide (attached below). Specifically, I don't see how the diagram for c1 shows a phase shift of positive 288 degrees. If, as suggested by c2, a phase shift of –18 degrees corresponds to a right shift of the rising edge by 5% of a cycle, then 288 degrees should correspond to a left shift of the rising edge by 80% of a cycle, which is not what is shown by the figure.  


Interestingly, Figure 17. of the LVDS SERDES IP Core User Guide for the Arria 10 and Cyclone 10 (also attached below) is a very similar diagram: the phase relationships between the output clocks are the same as in the first diagram, but the labeled phase shifts are different. This figure makes sense to me, as +18 degrees corresponds to a right shift of 5% of a cycle and 324 degrees corresponds to a right shift of 90% of a cycle.   


I would appreciate if someone could help me resolve my confusion here. Is Figure 9. inconsistent, or am I fundamentally misunderstanding something? 







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3 Replies

Hello there,

Actually you have to look at with respect to the reference clock , not with respect to the VCO clk. According to the user guide below , Table 12 : "signal interface between PLL IP core and ALT LVDS IP cores", Page 49.

c0 -> Serial clock -> (i.e fast clock which is with respect to the VCO) note in table 13 : Phase shift = –180° with respect to the voltage-controlled oscillator (VCO) clock

c1 -> load enable -> (i.e slow clock which is respect to reference clock )

c2 -> parallel clock ouput -> (i.e With respect to reference clock).


Can you have a look and let me know if you have questions ?

Hope helps .


Thank you ,





Hi Sree,


Thanks a lot for the reply. I think that I understand the table in the guide. My issue is with the diagram in Figure 9, which is attached to my first message. The rising edges shown are not consistent with the labeled phases. I later found another diagram in the Cyclone V handbook, which I've attached below (Figure 5-4). Notice that this diagram has the same phase labels as Figure 9 in the ALTLVDS IP Core guide but the rising edges of the clock signals are in different locations. For example, the load enable clock rises between bit 9 and 10 in the IP Core guide's figure, but it rises between bit 8 and bit 9 in the Cyclone V handbook figure. Using the figure from the Cyclone V guide, I was able to understand how to configure the external PLL properly; things appear to be working for me now.


But, I believe Figure 9 in the ALTLVDS IP Core guide is incorrect. At the very least it is inconsistent with the diagram in the Cyclone V handbook. This is what led to my initial confusion.






Thank you for the input Aaron, I am glad that you issue is resolved , Let me close the case.