Probelm with the simulation wave form of my counter fifo

[Sijith]

I am opening this new thread based on the suggestion from the intel community help. If you feel some more information needed please refer the message thread (please click here). 

I was trying to simulate my design that is created using Platform Designer System.  I have a counter module counter.v which is converted to a custom IP and I integrated that with an Avalon FIFO IP in platform designer system. But the simulation waveform outputs of the counter.v and counter + Avalon FIFO IP looks different. (please see attachments Capture_wave_counter.PNG and Capture_wave_counter_fifo.PNG)

When I simulate just counter module (using counter_tb.v, that I attached in previous message thread message)  the wave form of the data output (avalon_data) behaves as normal (have starting value 00000000000000000000000000000001) and starts the data with 32b'1 (please see attached Capture_wave_counter.PNG). But at the same time, when I simulate the counter_fifo with the testbench counter_fifo_tb.v . The fifo_0_out_readdata looks something different than the  and the first entry is `00000001000000000000000000000000` (looks like counting started from the 8th bit. Please see the picture Capture_wave_counter_fifo.PNG). Also please see Counter_fifo_wave_1.PNG

Is it something to do with the FIFO parameter setting? You can see from the Counter_FIFO/counter_fifo.qsys file the parameters I used (also see the attached counter_fifo_qsys.PNG). I am just wondering that setting channel width parameter =8 in Avalon-ST Port settings of FIFO IP has to do something with this? (as you can see in counter.v, there is no signal named "channel" defined in it). I read from the FIFO IP manual that 'channel" signal is not mandatory one, and would like to make sure that the did not make any difference here.

The working directory is attached as Counter_FIFO . It contains counter.v and counter_tb.v for simulating just counter module . For simulating counter fifo design please see ../Counter_FIFO/counter_fifo/sim/counter_fifo_tb.v and the .do file used for the simulation is  ../Counter_FIFO/counter_fifo/sim/mentor/sim.do 

(I compiled the whole design in Quartus Prime Pro and using Arria 10 device. To get the counter fifo design, I have added the counter custom IP and  Avalon FIFO IP in the IP in the Platform Designer)  

[RichardTanSY_Intel]

Thank you for reaching out. I want to assure you that I have received your request and will thoroughly investigate it. However, I am currently handling a few important tasks that require immediate attention.

Please know that your case is a priority for me, and I will allocate dedicated time to address it as soon as possible.

I appreciate your patience and understanding in the meantime.

If there are any urgent updates or any additional information you would like to share, please feel free to let me know.

I will make it a point to respond promptly.

[RichardTanSY_Intel]

Just a quick update to let you know that I'm still actively investigating the issue. I understand the importance of resolving it and I'm dedicated to finding a solution.

I'll keep you informed of any progress made. Thank you for your patience.

Best Regards,

Richard Tan

[RichardTanSY_Intel]

Please allow me more time to look into this.

[RichardTanSY_Intel]

Sorry for the delay in response.

I believe the "channel width" parameter in the Avalon-ST port settings of the FIFO IP can potentially cause the simulation waveforms of the counter module and the integrated counter + Avalon FIFO IP to appear different.

The "channel width" parameter determines the width of the data channel in the FIFO, specifying the number of bits in each data element that can be read or written. If the channel width is set differently between the counter module and the FIFO IP, it can result in misalignment or reinterpretation of the data.

In your case, as the counter module produces 32-bit data but the FIFO IP's channel width is set to 8 bits, the FIFO will treat the 32-bit data as four separate 8-bit data elements. This can lead to the waveform discrepancy you observed, where the FIFO output starts counting from the 8th bit instead of the first bit.

Hope that helps to explain.

Btw, I have trouble duplicate the simulation, could you help to provide the simulation flow/steps/script to replicate it?

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey. 

[RichardTanSY_Intel]

Any update on this?

Best Regards,

Richard Tan

[RichardTanSY_Intel]

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding. If you have any further questions or concerns, please don't hesitate to let us know. Thank you for reaching out to us!

Best Regards,

Richard Tan

p/s: If you find any answers from the community or Intel Support to be helpful, we encourage you to mark them as the best answer or rate them 4/5 in the survey.