Verilog .v and.vp on zip file to Qsys

[dicas3d]

I got a model in Verilog from my development board's SDRAM controller controller manufacturer. The model comes in a file. zip that contains a file. .vp and a .vp file. How to convert to an Qsys component?

[dicas3d]

I think that I need to use modelsim or another simulation software to do the task. Can anyone who knows confirm? I don't tryed yet because just on Monday I have access to the computer with the Quartus prime lite and the project that I'm working.

[SyafieqS]

You issue seem to be related to the encryption.

You may look into below link for detail.

There is discussion on encrypted Verilog.

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Decrypt-verilog-file/td-p/1383551

[dicas3d]

Yes, maybe. But in my particular case I even don't know if I need any key and I'm in doubt if I'm capable of working with the model without NC-Verilog because it's payed. To check it better the model is the provided in link https://www.winbond.com/hq/product/specialty-dram/sdram/?__locale=en&partNo=W9864G6JT . Does Intel Quartus Prime Lite allow precompiled Verilog models to be used as components? If yes, I can try compiling on edaplayground which has NC-Verilog.

[FvM]

Hello,
not completely clear what you are trying to achieve. The RAM model is for simulation only. Typically you connect it in the simulation top level (test bench) to your design under test.

[dicas3d]

From what I've researched so far there is no ready IP Core available for QSYS for this SDRAM controller. What I'm trying to do is to solve this. Even the manufacturer sends this when asked about it. So what I'm trying to do is use the model as/convert the model to the IP Core. As I know in Quartus Prime pro we can execute simulation models inside a component to do it called Generic Component.

[SyafieqS]

Speaking of generic type, you can refer to below doc for more detail. Platform Designer allows you to add generic components with the implementation defined in _hw.tcl (IP type), in an HDL file (HDL type), in high level synthesis files (HLS type), or with only a partially defined implementation (Blackbox type).

https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/creating-generic-components-in-a-system.html

I believe this is what you are looking for.

[SyafieqS]

Let me know if there is any update

[dicas3d]

This tutorial is only applicable in the pro version, but I managed to get an SDRAM controller working on my system and version ported from an old version.

[SyafieqS]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

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