Hey guys,
i am trying to simulate the ddr2 sopc controller using the method provided, by making a wrapper file using the example top level design. The design passes the analysis and synthesis test, though the fitter gives an error,
"Internal data size overflow in module "ddr2_test_component_ram_module".
This is the test ddr2 module used for simulation. When i see the code for this i know that its data width is 128 bits. i guess the controller gives me 64 bit data width. now I am not very sure how to change either of them so to match the data widths.
Any suggestions.
Many thanks,
-M
