FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6568 Discussions

Problem in signal compiler

Altera_Forum
Honored Contributor II
‎10-08-2008 02:57 AM
1,034 Views

when i double click on signal compiler on my model and perform the step 1, 2, 3 to generate VHDL code, synthesize and download to Altera DSP board (Cyclone II EP2CS5) , all the program related to the project will jammed. And it happen when i click on the compile button. but this problem will not happen when i use the pc in other workstation.  

 

is this because of my matlab or quartus configuration problem?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.