Problem running pin_assignments.tcl script with uniPHY DDR3 controller

[Altera_Forum]

Hi, 

 I'm experiencing some problems with SoPC builder and quartus 11.0.   Why SoPC builder and not Qsys ? Because I use an IP that is'nt yet avaible with Qsys...   I did a very simple project with SoPC buider : For a Stratix IV device : - Nios II processor - DDR3 controller with uniPHY   Building the system with SoPC builder is OK. Analysis & Synthesis are OK. After that I did : Tools -> Tcl scripts, then I selected and launched <>_pin_assignments.tcl script.   Here is the log (tcl console) :  ERROR: Argument <node_object> is an object filter that matches no objects. Specify one matches only one object. while executing "get_node_info -cell $node_id" (procedure "is_node_type_pll_clk" line 2) invoked from within "is_node_type_pll_clk $pll_output_node_id" (procedure "get_input_clk_id" line 2) invoked from within "get_input_clk_id $pll_ck_clock_id" (procedure "ddr3top_p0_get_ddr_pins" line 237) invoked from within "ddr3top_p0_get_ddr_pins $instname allpins" (procedure "ddr3top_p0_initialize_ddr_db" line 13) invoked from within "ddr3top_p0_initialize_ddr_db ddr_db" (file "D:/dev_fpga/test_ddr3_11/sopc/ddr3top/altera_mem_if_ddr3_phy/ddr3top_p0_pin_assignments.tcl" line 191)    If someone has an idea... Similar projects worked well with the same procedure with Quartus 10.1...   Thank you.

[Altera_Forum]

Hi,  

if you built your design in older Quartus and migrated the project there might be changes in the generated top level look over the connections

[Altera_Forum]

Hi, 

I create the project with Quartus 11. It isn't a migrated project ;)

[Altera_Forum]

Hi, 

I have exactly the same problem except that I am using Qsys. But I have the same error. Need help please! Cheers, C.

[Altera_Forum]

Ok, It's not just me :cry:. 

 I switched back to quartus 10.1...

[Altera_Forum]

I also have exactly the same error with Q11.0 UniPhy DDR3. 

 Making me very sad...

[Altera_Forum]

BTW, I also get a whole bunch of critical warnings before this event all roughly similar to : 

  Critical Warning: Could not find pin of type ck_pins from pattern uniPHY_group_inst|master_phy_top|uniphy_master_inst|p0|controller_phy_inst|memphy_top_inst|umemphy|uio_pads|uaddr_cmd_pads|clock_gen[*].uclk_generator|pseudo_diffa_0|o  but with various different paths.

[Altera_Forum]

Aha - I think I have found it. It is basically the same problem as described in solution rd05232011_576. (Search for this on the Altera website). I would post a link but the forum won't let me :-(. 

 It is not EXACTLY the same problem, but I have changed the std_logic_vector(0 downto 0) to std_logic in the component definition for the verilog sub-entity, and changed the mappings to the form:  mem_ck => mem_ck(0).  I hope this helps

[Altera_Forum]

Did you succeed to run the pin_assignment.tcl script without any errors?

[Altera_Forum]

Yes. It ran without error after the changes although I still receive one critical warning that I am having a look at (there were 9 before the changes).

[Altera_Forum]

Thank You, It works. 

 - Replace, std_logic_vector (0 downto 0) by std_logic for : mem_cas_n mem_ck mem_ck_n mem_cke mem_cs_n mem_odt mem_ras_n mem_we_n - Replace, for all the above signals, mem_(0) by mem_x

[Altera_Forum]

Here is an example of a Python script which can do all the job for you, just replace the path and the name of your top level entity generated sy SoPC builder : 

  f = open('./src/sopc/your_sopc_top_level.vhd') text = f.read() f.close() new_text = text.replace("mem_cas_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_cas_n : OUT STD_LOGIC;") new_text = new_text.replace("mem_ck : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_ck : OUT STD_LOGIC;") new_text = new_text.replace("mem_ck_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_ck_n : OUT STD_LOGIC;") new_text = new_text.replace("mem_cke : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_cke : OUT STD_LOGIC;") new_text = new_text.replace("mem_cs_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_cs_n : OUT STD_LOGIC;") new_text = new_text.replace("mem_odt : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_odt : OUT STD_LOGIC;") new_text = new_text.replace("mem_ras_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);", "mem_ras_n : OUT STD_LOGIC;") new_text = new_text.replace("mem_we_n : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)", "mem_we_n : OUT STD_LOGIC") new_text = new_text.replace("mem_cas_n(0)", "mem_cas_n") new_text = new_text.replace("mem_ck(0)", "mem_ck") new_text = new_text.replace("mem_ck_n(0)", "mem_ck_n") new_text = new_text.replace("mem_cke(0)", "mem_cke") new_text = new_text.replace("mem_cs_n(0)", "mem_cs_n") new_text = new_text.replace("mem_odt(0)", "mem_odt") new_text = new_text.replace("mem_ras_n(0)", "mem_ras_n") new_text = new_text.replace("mem_we_n(0)", "mem_we_n") f = open('./src/sopc/your_sopc_top_level.vhd', 'w') f.write(new_text) f.close()