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Altera_Forum
Honored Contributor I
718 Views

LF LFSR simulation get zero values in DSP Builder

Hi, 

i'm implementing an LFSR whith leap forrward. I import the code im dsp builder using HDL import then i try to simulate it in dsp builder but when i export the data to matlab i just get zero values. 

The simulation works with modelsim. 

this is the code: 

library ieee; 

use ieee.std_logic_1164.all; 

use ieee.numeric_std.all; 

use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity lfsrlp14B is 

generic 

( SIZE: natural := 14 

); 

 

port 

clk: in std_logic; 

s_out: out std_logic_vector((14-1) downto 0) 

 

); 

 

end entity; 

 

architecture shiftreg of lfsrlp14b is 

signal temp_sr : std_logic_vector((SIZE-1) downto 0):="10100000000100"; 

begin 

process(clk)  

begin 

if(rising_edge (clk)) then 

for n in 0 to (SIZE-2) loop 

 

temp_sr(n) <= temp_sr(n+1); 

temp_sr(0) <= temp_sr(0) xor temp_sr(7) xor temp_sr(9) xor temp_sr(11); 

temp_sr(1) <= temp_sr(1) xor temp_sr(8) xor temp_sr(10)xor temp_sr(12); 

temp_sr(2) <= temp_sr(2) xor temp_sr(9) xor temp_sr(11)xor temp_sr(13); 

temp_sr(3) <= temp_sr(0) xor temp_sr(3) xor temp_sr(7) xor temp_sr(9) xor temp_sr(10) xor temp_sr(11)xor temp_sr(12); 

temp_sr(4) <= temp_sr(1) xor temp_sr(4) xor temp_sr(8) xor temp_sr(10)xor temp_sr(11) xor temp_sr(12)xor temp_sr(13); 

temp_sr(5) <= temp_sr(0) xor temp_sr(2) xor temp_sr(5) xor temp_sr(7) xor temp_sr(12) xor temp_sr(13); 

temp_sr(6) <= temp_sr(0) xor temp_sr(1) xor temp_sr(3) xor temp_sr(6) xor temp_sr(7) xor temp_sr(8) xor temp_sr(9) xor temp_sr(11)xor temp_sr(13); 

temp_sr(7) <= temp_sr(0) xor temp_sr(1) xor temp_sr(2) xor temp_sr(4) xor temp_sr(8) xor temp_sr(10)xor temp_sr(11)xor temp_sr(12); 

temp_sr(8) <= temp_sr(1) xor temp_sr(2) xor temp_sr(3) xor temp_sr(5) xor temp_sr(9) xor temp_sr(11)xor temp_sr(12)xor temp_sr(13); 

temp_sr(9) <= temp_sr(0) xor temp_sr(2) xor temp_sr(3) xor temp_sr(4) xor temp_sr(6) xor temp_sr(7) xor temp_sr(9) xor temp_sr(10)xor temp_sr(11) xor temp_sr(12) xor temp_sr(13); 

temp_sr(10) <= temp_sr(0) xor temp_sr(1) xor temp_sr(3) xor temp_sr(4) xor temp_sr(5) xor temp_sr(8) xor temp_sr(9) xor temp_sr(10)xor temp_sr(12) xor temp_sr(13); 

temp_sr(11) <= temp_sr(6) xor temp_sr(0) xor temp_sr(1) xor temp_sr(2) xor temp_sr(4) xor temp_sr(5) xor temp_sr(6) xor temp_sr(7) xor temp_sr(10) xor temp_sr(13); 

temp_sr(12) <= temp_sr(0) xor temp_sr(1) xor temp_sr(2) xor temp_sr(3) xor temp_sr(5) xor temp_sr(6) xor temp_sr(8) xor temp_sr(9); 

 

end loop; 

temp_sr((SIZE-1)) <= temp_sr(1) xor temp_sr(2) xor temp_sr(3) xor temp_sr(4) xor temp_sr(6) xor temp_sr(7) xor temp_sr(9) xor temp_sr(10); 

 

end if;  

end process; 

s_out <= temp_sr; 

 

end shiftreg;  

 

Please Help me, i need this.
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1 Reply
Altera_Forum
Honored Contributor I
24 Views

Try a simple code first, like outputting a constant value, and see what you get in Matlab. That way you will know if the problem comes from the code or the export function to Matlab. I've never worked with DSP builder in conjunction with Matlab so I can't help you further. 

 

Your loop is rather strange... It looks like you are trying to write a software algorithm in HDL, and it won't work that way. One important thing about VHDL signals is that when you do a <= assignment in a process, the signal will only get the new value after the process is completed and only the last assignment done on a signal is actually taken into account. This means that:[list] 

[*] the line temp_sr(n) <= temp_sr(n+1); is useless, as the value is overwritten in the following lines 

[*] the loop is useless, because you are just doing 13 times the same thing[/list] 

I suggest first thinking about how this LFSR function would be done in hardware, and then write some HDL code that describes it.