Problem with altpll output

[Altera_Forum]

I use EP2C8Q, the input clock connect the clk3 pin. the frequency is 27MHZ, I want to get higher frequency clock. I use the altpll to multiplier. The multiplication is 2 and 4. When I measure the output clock, I find the frequency is very unstable, and so is the locked signal. The Pll Summary is below: 

   PLL mode Normal Compensate clock clock0 Self reset on gated loss of lock Off Gate lock counter -- Input frequency 0 27.0 MHz Input frequency 1 -- Nominal PFD frequency 27.0 MHz Nominal VCO frequency 755.9 MHz VCO post scale -- VCO multiply -- VCO divide -- Freq min lock 17.86 MHz Freq max lock 35.71 MHz M VCO Tap 0 M Initial 1 M value 28 N value 1 Preserve counter order Off PLL location PLL_1 Inclk0 signal CLK Inclk1 signal -- Inclk0 signal type Dedicated Pin Inclk1 signal type --     Anybody who knows the reason? Thanks!

[Altera_Forum]

Did you connect the VCCA_PLL_x Pins directly to 1,2V Core supply or as Altera recommends via an inductor (ferrit) and some decoupling caps ? 

 As you use q QFP package, what about your layout ?  Do you have an impedance controlled powersupply ?  As your clock is 27x4=108 MHz you must take at least the 3. harmonic = 324MHz into consideration that your power supply will have a low Z up to 324MHz to control the voltage ripple Are the traces vor the PLL power supply very short, directly connected to the power supply or are they close to traces with noise ? this would lead to a modulation and might be the source of your unstable DPLL  What speed grade do you use ?  the output of your pll is connected to a dedicated clock pin "PLL?_OUTp" ?

[Altera_Forum]

Pll_out connection isn't critical in this regard. PLL power supply is most critical, as said, also signal quality of clock input. Also a large amount of simultanaeous switching FPGA outputs can promote PLL loss of lock.

[Altera_Forum]

--- Quote Start ---  Did you connect the VCCA_PLL_x Pins directly to 1,2V Core supply or as Altera recommends via an inductor (ferrit) and some decoupling caps ?   As you use q QFP package, what about your layout ?  Do you have an impedance controlled powersupply ?  As your clock is 27x4=108 MHz you must take at least the 3. harmonic = 324MHz into consideration that your power supply will have a low Z up to 324MHz to control the voltage ripple Are the traces vor the PLL power supply very short, directly connected to the power supply or are they close to traces with noise ? this would lead to a modulation and might be the source of your unstable DPLL   What speed grade do you use ?  the output of your pll is connected to a dedicated clock pin "PLL?_OUTp" ?  --- Quote End ---     I think the layout is the most possible reason, I didn't consider these in my PCB board. And I didn't connect the output pll to the pin "PLL_out", is this necessary? Thank you

[Altera_Forum]

Connecting PLL outputs through dedicated "pll_outxx" pins reduces the jitter. It's recommended, when low jitter is a design objective. But it's not generally required. In some designs, e.g. DDR RAM controller, regular IO is preferred for clock outputs to achieve particular timing constraints.