Problem with feedback connection

[Altera_Forum]

Hi everyone, 

I have make a simply firmware in dsp builder but have some problem in feedback connection. If i run a simulation in simulink I haven't any kind of problem, these arise after the download in FPGA. I have another answer: The divider block have a particular latency??? The operations frequency of first part of firmware is 300MHz, this is a problem with the bus width of someone data??? I attach the file model of simulink that i have created for test purpose, please control it and give me any kind of information about my error. Thanks for your attention and sorry for my english. Bye bye :cool:

[Altera_Forum]

In my ipinion,your clock divider needs dealing.Dew to a time question.

[Altera_Forum]

Hi, thanks for this hint but the problem isn't the clock divider but the arithmetic operand divider, and a feedback on the subtractor. 

Bye byw

[Altera_Forum]

Hi everyone, maybe I'm not clear about the trouble founded in the test model create by me via DSP BUILDER. 

I have two questions: 1) If the firmware work @300MHz the latency of block divider is less than the clock period?? 2) There are some possible truble about a feedback connection in the subtractor node??? I make this two answer because i haven't considerate the divider latency in test project and i think that there is no problem in feedback connection but when i "program" FPGA i found out of the subtractoru 1 e -1 instead of 0. Again thanks for attention and sorry for my english. Bye Bye at all

[Altera_Forum]

come from china ?

[Altera_Forum]

--- Quote Start ---  come from china ?  --- Quote End ---    what???? But why you have maked this answer?????????:confused:

[Altera_Forum]

--- Quote Start ---  what???? But why you have maked this answer?????????:confused:  --- Quote End ---   i am sorry i just guess