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Has anybody successfully used the DDR2 High Performance Controller in Quartus 9.1? I'm getting compilation errors when the SDC script runs because it can't find certain logic in the datapath. Looking at the design heirarchy, the logic is truly not being implemented.
JakeLink Copied
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I'm simply trying to find the documentation for it - all the links on the Altera website connect to the DDR3 pdf.
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Yes there doesn't appear to be updated documentation available yet. I did resolve my issue however. I was doing a test project and only wanted to use 8-bits of my 64-bit SoDIMM. Apparently the Core does not like to be told that it's an 8-bit DIMM. So I went back and told it that it was a discrete component and everything worked fine.
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Well, my point is that currently the "DDR and DDR2 SDRAM High-Performance Controller MegaCore Functions" page located here:
http://www.altera.com/products/ip/iup/memory/m-alt-hpddr2.html?gsa_pos=1&wt.oss_r=1&wt.oss=ddr2 high speed has links entitled "View Literature" and "ddr and ddr2 sdram high-performance controller user guide (pdf) (http://www.alteraforum.com/literature/ug/ug_ddr_ddr2_sdram_hp.pdf)" which both point to the DDR3 pdf file. I think this is a mistake. I'm having trouble finding the original high speed DDR and DDR2 documentation.- Mark as New
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Yeah I'm not having the same problem. Here you go:
http://www.altera.com/literature/ug/ug_ddr_ddr2_sdram_hp.pdf Jake- Mark as New
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I just got an email from the FAE. Looks like Altera is trying to collect all the memory interface info into one place:
http://www.altera.com/literature/lit-external-memory-interface.jsp Looks like all updated documents are there. Jake- Mark as New
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This is a great advance!
--- Quote Start --- I just got an email from the FAE. Looks like Altera is trying to collect all the memory interface info into one place: http://www.altera.com/literature/lit-external-memory-interface.jsp Looks like all updated documents are there. Jake --- Quote End ---- Subscribe to RSS Feed
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