Qsys Hard IP implementation. A couple of questions.

Altera_Forum · ‎12-13-2011

I've been using the example Cyclone iV PCIe design here...

http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs

..as the basis of a job for a while but am trying to start from scratch to optimise the design.

1) What do you do with all the 'unused' signals that are generated in the Qsys PCIe component? The PCIe user guide says they should be exported, but what are they connected to?

I'm talking about inputs like "pcie_hard_ip_0_pipe_ext_rxvalid0_ext". In the example design above this isn't connected at the top level....

q_sys u0 (

.clk_clk (clk50),

.reset_reset_n (pcie_rstn),

.pcie_hard_ip_0_refclk_export (refclk),

.pcie_hard_ip_0_test_in_test_in (test_in),

.pcie_hard_ip_0_pcie_rstn_export (pcie_rstn),

.pcie_hard_ip_0_reconfig_busy_busy_altgxb_reconfig (busy),

.pcie_hard_ip_0_test_out_test_out (test_out_icm),

.pcie_hard_ip_0_rx_in_rx_datain_0 (rx_in0),

.pcie_hard_ip_0_tx_out_tx_dataout_0 (tx_out0),

.pcie_hard_ip_0_reconfig_togxb_data (reconfig_togxb),

.pcie_hard_ip_0_reconfig_fromgxb_0_data (reconfig_fromgxb),

.pcie_hard_ip_0_fixedclk_clk (clk125),

.pcie_hard_ip_0_pipe_ext_pll_powerdown (~pcie_rstn),

.pcie_hard_ip_0_pipe_ext_gxb_powerdown (~pcie_rstn),

.pio_led_out_export (user_led),

.pio_pb_in_export (user_pb),

);

...but it's in the generated Qsys module as an input. In VHDL it can't be left unconnected so what do you do with it?

2) In the example design the two signals "reconfig_togxb" and "reconfig_fromgxb" aren't declared. A bif of googling shows in verilog this means they're created as 1 bit wires so the altgx_reconfig module isn't

properly connected to the PCIe core.

Does this need corrected?

Thanks for any pointers,

Nial.

Altera_Forum · ‎02-27-2013

Hello, GZoinker!

Did You find the answer to the above?

Altera_Forum · ‎02-27-2013

Look at the code in this thread:

http://www.alteraforum.com/forum/showthread.php?t=35678

Cheers,

Dave