Qsys custom IP component for Maxim MAX1304/08/12 ADC

[Altera_Forum]

Greetings, 

I am trying to integrate MAXIM MAX1304 ADC to NIOS in a Cyclone 3, it is working for the most part. I was wondering if I could get an expert review from gurus in this forum and see if we could increase the FIFO depth somehow.  My system uses Cyclone III EP3C10F256 FPGA and there is other stuff in it as well including a NIOS economy core. Originally I had FIFO depth 64 and NIOS onchip boot memory 32K. I realized that the bootloader is only taking 16K so I could reduce memory size it and there will be space left to increase the FIFO depth. Obviously I don't understand this because reducing onchip memory to 20K reduced total memory bits while increasing FIFO depth to 128 samples increased total logic element usage.  With onchip memory 20K and ADC FIFO depth 128 samples, I am at 92% LE & 44% RAM bits consumption.  Now my question to the gurus in here, is there a way to use available ram bits for FIFO instead of logic elements? I am asking this because if changing onchip memory size affects total ram bits, why can I not use the same ram bits to build my FIFO because in theory a FIFO is a 15 bit wide 128 sample deep piece of memory anyway, right?  Thanks in advance,  Hasan Rizvi

[Altera_Forum]

Hi Hasan: 

 I've looked at your code, and there's a few things I'm seeing:  1: Your Fifo logic is intermixed with your state machine logic. It's better to separate the memory into it's own module, so that you can control the synthesis a little better.  2: Your defininition of fifo_data_array, has a non- power of 2 size. 129 location (128:0) This may cause the synthesis engine to not reference a memory.  3: I was taught that memories should be defined as reg [14:0] data_fifo_array[0:127]. This makes a difference when you are pre-filling the memory with a $readmemh, so it may be causing the synthesis tool to not properly identify the memory as well.  4: (Optional). I tend to make the size of the fifo fit the memory block size for that bit width. Since you are using a Cylone 3 family, for 15 bits of data, the "Optimal" size would be 512 locations. Based on http://www.altera.com/literature/hb/cyc3/cyc3_ciii51004.pdf page 2 (512x16 or 512x18)  Hope this helps.   Pete www.infinetix.com

[Altera_Forum]

Hi Anakha, 

Thank you very much for your reply. Your suggestions are very helpful and I will separate the FIFO memory module from the adc module and this should really help utilizing M9k memory blocks instead of logic elements. I can even get a deeper FIFO this way.  Regards,  Hasan

[Altera_Forum]

Glad to help.. 

 Here's the Altera recommended coding style for synthesis. It's helpful for making sure the memory block gets implemented as you entended.   http://www.altera.com/literature/hb/qts/qts_qii51007.pdf  Pete