I'm using the Qsys Pcie to DDR3 reference design that's available on the altera website. With that I'm using a jungo driver and the pcie simple sw example that's posted on the alterawiki. The reference design uses the mSGDMA design that's also up on the altera wikiI'm trying to transfer data from a file downto the onboard DDR3 memory and the reverse under the host PC control. So I'm modifying the dma_write and dma_read functions and confused about the descriptor and direction control. There's no difference between a write descriptor and a read descriptor except in the target read and write address. A write operation sets the read address to the physical address down on the DDR3 and the write address to host memory. A read operation sets the read address to a host memory location and the write address to DDR3 space. The descriptor is written down to the dispatcher in the SGMDA where it's put on the read and write FIFOs - even though I only wanted a read or a write, not both. The net effect is that when I do a DMA_read, expected data is transferred to the DDR3 memory and then read back. When I do a DMA_write, it appears that data is written line by line to the DDR3 and then transferred back via a DMA operation. This is all great for a demo but not quite what I wanted. I know in one of the text files for the mSGDMA it mentions the design is copying to AND from memory. So, three questions: 1. Has anyone modified the mSGDMA to distinguish between a read and a write descriptor? a. There's a "MODE" variable in the descriptor_buffers.v file that has some control over pushing onto the read and write descriptors - should this be changed to read a value out of the descriptor field? b. Should there be two "go bits' - one for read and one for write? 2. Should I just rename DMA_write to DMA_read (and vice versa) in the software program and ditch the slavewrite and slave reads that seem to be transferring expected data? 3. If I'm using the DMA read function, should I just set the write address to an unused memory space on the DDR3? Dave Smith
I have not yet tried it but...1. Has anyone modified the mSGDMA to distinguish between a read and a write descriptor? >> it is possible to have set of mSGDMA for each dedicated direction. >> just make 3 components for each directions, read master, write master, and dispatcher 2. Should I just rename DMA_write to DMA_read (and vice versa) in the software program and ditch the slavewrite and slave reads that seem to be transferring expected data? >> as noted above, you need to have 2 sets. 3. If I'm using the DMA read function, should I just set the write address to an unused memory space on the DDR3? >> as far as I know, the DDR3 does not accept 2 access at a time. >> it means, only read or write operation can be done at a time. >> if write happens after the read, any address should be fine.
Dual read and write FIFOs are only used when the descriptor block is setup for MM to MM transfers. They are needed so that the read and write portions of the descriptor are buffered independently so that the read and write master can operate independently (i.e. the write master doesn't block the read master).If you want to implement a read or write only mSGDMA you need to switch the dispatcher over to MM-->ST or ST-->MM and only connect one of the master blocks to the dispatcher. So if you wanted to do something like read data over PCIe from the host's main memory then pump the data into some sort of data streaming block you would configure the mSGDMA for MM--ST and not bother writing the write_address value in the descriptor since there is no destination address in that example. I'm not sure how you would modiy the PCIe reference design host code to do this but it should be fairly straight forward if you look at the Nios II driver that is bundled with the dispatcher block.