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Altera_Forum
Honored Contributor I
1,083 Views

Quartus 16: Can't find port "reset" in OpenCore Plus entity "alt_vip_cvo_core"

Hello, 

 

I get the following error message after upgrading a design from Quartus 15.1 to 16.0: 

 

Error (12097): Can't find port "reset" in OpenCore Plus entity "alt_vip_cvo_core". -- OpenCore Plus specification file is invalid 

 

The CVO is part of a QSYS design. The QSYS file generates without problem. 

 

The whole design builds ok in Quartus 15.1. I cleaned the project and removed temporary files before compiling on 16. 

 

Is this a known problem? Does anyone know a way to fix this? 

 

Thank you, 

Klaus
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2 Replies
Altera_Forum
Honored Contributor I
124 Views

I have exactly the same problem in quartus II 16.0, when using Clocked Video Output II(4K Ready), 

 

I have found interesting phenomenon, the Qsys generates HDL faster than it should be, the CVO II must be broken.:( 

 

I switch to previously Clocked Video Output (NOT II), problem solved.:-P 

 

And the VIP User Guide is a mess. It has no RO or RW descriptions at all, people are blind guessing which is writable which is readonly, and what order it should be updated.:mad: 

 

Beware, you need the TPG to be able to full fill your CVO FIFO, otherwise the timing of VS HS are scrambled, you might get out of range warring on your monitor. For example, if you need 1080p@60Hz output, the clock for TPG must be greater than 130MHz, there is a simple equation for that. 

 

I didn't foresee this, so it wasted my two days of time to dig around. 

 

The CVO won't start clocking out unless the FIFO is full filled, the time consumed by 1920 pre FIFOed pixels +130Mhz clock filling 1079 lines must be less than the time to running out the buffer at 148.5MHz. 

 

1920 * 1 / 148.5MHz + ( (44 + 88 + 148 + 1920) * 1 / 148.5MHz * (1080 + 4 + 5 + 36) - 1920 * 1080 * 1/ 130MHz) the result must stay in positive. 

 

Good luck. 

 

Updated 20160623: The Clocked Video Input II can't be used either under evaluation license.:( CVI(not II) is OK. 

 

Warning (115003): Can't generate programming files for your current project because you do not have a valid license for the following IP core or cores. 

Warning (115004): Unlicensed encrypted design file: "D:/FPGA/NRX/cpu/synthesis/submodules/src_hdl/alt_vip_cvi_av_st_output.sv" 

Warning (115004): Unlicensed encrypted design file: "D:/FPGA/NRX/cpu/synthesis/submodules/src_hdl/alt_vip_cvi_resolution_detection.sv" 

Warning (115004): Unlicensed encrypted design file: "D:/FPGA/NRX/cpu/synthesis/submodules/src_hdl/alt_vip_cvi_sync_polarity_convertor.v" 

Warning (115004): Unlicensed encrypted design file: "D:/FPGA/NRX/cpu/synthesis/submodules/src_hdl/alt_vip_cvi_core.sv" 

Warning (115004): Unlicensed encrypted design file: "D:/FPGA/NRX/cpu/synthesis/submodules/src_hdl/alt_vip_cvi_sync_conditioner.sv" 

Warning (115004): Unlicensed encrypted design file: "D:/FPGA/NRX/cpu/synthesis/submodules/src_hdl/alt_vip_cvi_register_addresses.sv" 

Warning (115004): Unlicensed encrypted design file: "D:/FPGA/NRX/cpu/synthesis/submodules/src_hdl/alt_vip_cvi_sync_align.sv" 

Warning (115004): Unlicensed encrypted design file: "D:/FPGA/NRX/cpu/synthesis/submodules/src_hdl/alt_vip_cvi_control.sv" 

Warning (115004): Unlicensed encrypted design file: "D:/FPGA/NRX/cpu/synthesis/submodules/src_hdl/alt_vip_cvi_sample_counter.v" 

Warning (115004): Unlicensed encrypted design file: "D:/FPGA/NRX/cpu/synthesis/submodules/src_hdl/alt_vip_cvi_write_buffer_fifo.sv" 

 

update:2016/6/29 Switch II(4k Ready) is unusable too, in Q16.0, Switch I is OK. 

 

Error (12002): Port "din_data" does not exist in macrofunction "swi_0" 

Error (12002): Port "din_endofpacket" does not exist in macrofunction "swi_0" 

Error (12002): Port "din_ready" does not exist in macrofunction "swi_0" 

Error (12002): Port "din_startofpacket" does not exist in macrofunction "swi_0" 

Error (12002): Port "din_valid" does not exist in macrofunction "swi_0" 

Error (12002): Port "dout_data" does not exist in macrofunction "swi_0" 

Error (12002): Port "dout_endofpacket" does not exist in macrofunction "swi_0" 

Error (12002): Port "dout_ready" does not exist in macrofunction "swi_0" 

Error (12002): Port "dout_startofpacket" does not exist in macrofunction "swi_0" 

Error (12002): Port "dout_valid" does not exist in macrofunction "swi_0" 

 

------------------------------------------------------------------------------------------------------------------------------------------------------------ 

 

There is another issue about VIP, the Mixer II need 3 symbols per beat for input but with alpha enabled 4 symbols per beat are required, 

There is no clearly document described how the data struct will look like, so I have tried it out by myself. 

 

1. RGB 3 symbols with alpha channel disabled, R is the most significant symbol. 

2. URGB 4 symbols per beats with alpha channel enabled but Alpha Input Stream Disabled, U is the most significant symbol. U=Unused for color or alpha but control packet  

3. RGBA 4 symbols per beats with alpha channel enabled, R is the most significant symbol. 

 

I have spent a week to finish my own version of alpha generator including  

1. covert 3 symbols input stream into 4 symbols per beats stream, 

2. rearrange the control packet too, from 3 symbols to 4. 

3. drop all others data packets, otherwise it will be difficult to implement. 

4. several independent semi-transparent controls by specific color and alpha, for transparent glass effect. 

5. Swap URGB & RGBA, I think this is a bad design by ALTERA. 

 

I think ALTERA should have been integrate this color transparency function into Mixer II.
Altera_Forum
Honored Contributor I
124 Views

Hi, 

I have some problems on display port IP core. The Displa Port AUX interface have "aux_in,aux_oe,aux_out" signal. But on my Altera Arria10 SoC Development Kits, there have "DP_AUX_DE DP_AUX_D DP_AUX_REn DP_AUX_R" signal,how can I constraint the Display Port IP Core AUX signal to the FPGA Board?  

Thanks//BR
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