Quartus MSGDMA core Empty bits when used from Avalon ST to Memory Mapped transfer

[NGord]

On an Avalon-ST to Memory mapped DMA transfer, if Empty bits are set, on the Avalon ST bus, what happens to a 32 bit Memory mapped transfer, does the DMA just write the relevant bytes to memory?

[EBERLAZARE_I_Intel]

Hi,

Which exact settings are you referring to?:

https://www.intel.com/content/www/us/en/docs/programmable/683130/23-3/parameters-13423.html

[NGord]

Set DMA mode to Streaming to Memory mapped
Set to '32 bit data width' 
Set 'Packet Support Enable'
This will create two Empty bit signals for the Avalon-ST bus   which show which of the 4 bytes on the ST side carry valid data.
I want to know what the Memory mapped side does when it sees any of these Empty bits set.
Will it use the Byte enable signals to write only the relevant bytes or does it ignore Empty bit setting?

[EBERLAZARE_I_Intel]

Hi,

Thanks for the clarification, let me check with our internal team and get back to you. I would assume that the empty bits are filled, and ignored. (I may be wrong)

[EBERLAZARE_I_Intel]

Hi,

(i), for an Avalon -ST to a Memory mapped transfer, if I have one channel bit enabled, which can be set to a 0 or a 1, how does that manifest itself on the Memory mapped interface? Is it ignored?

For MSGDMA with Streaming to Memory-Mapped mode, the channel enabled option will be grey out means can’t be enabled. So I would say that’s right it’ll be ignored.

[NGord]

The above reply is on the wrong thread - please delete.

[EBERLAZARE_I_Intel]

Hi,

Empty bits signal is only available when Packet Support Enable is used. If check this note:

31.3.1.4. Parameters (intel.com)

Note: When PACKET_ENABLE parameter is disabled and TRANSFER_TYPE is not "Full Word Accesses Only", any unaligned transfer length will cause additional bytes to be written during the last transfer beat of the Avalon® streaming data source port of the read host core. Only with this parameter set TRUE, actual bytes transferred is meaningful for the transaction. So I would say that DMA will just write the relevant bytes to memory

Quartus MSGDMA core Empty bits when used from Avalon ST to Memory Mapped transfer On an Avalon-ST to Memory mapped DMA transfer, if Empty bits are set, on the Avalon ST bus, what happens to a 32 bit Memory mapped transfer, does the DMA just write the relevant bytes to memory?

Based on RTL and simulation, empty bits will be written to FIFO when EOP is high.

[NGord]

Surely you can recognise that my question hasn't been answered correctly?
Copying again rom above:
Set DMA mode to Streaming to Memory mapped
Set to '32 bit data width' 
Set 'Packet Support Enable'
This will create two Empty bit signals for the Avalon-ST bus   which show which of the 4 bytes on the ST side carry valid data.
I want to know what the Memory mapped side does when it sees any of these Empty bits set.
Will it use the Byte enable signals to write only the relevant bytes or does it ignore Empty bit setting?

[ShengN_Intel · Accepted solution]

Hi,

If using the Packet Support Enable feature, Empty bits signal will be available. With this feature enabled, actual bytes (no additional bytes) will be transferred for the transaction. So I would say that DMA will just write the relevant bytes to memory as mentioned before.

Thanks,

Sheng

[EBERLAZARE_I_Intel]

Hi,

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