Query on PCIe DMA Engine

[mrama13]

We have added DMA Engine to the existed PCIe Hard IP Core, changed the design according to DMA (Interface-2X4,128,125MHz, Address width-64(DMA Supports)) and try to do transactions with the external devices.

Here in modified, have configured BAR4(Base address register) for RD/WR Transactions with device.

• I can’t able to configure BAR0 Register for transactions as existed, if we enable Internal descriptor (because BAR0 is internally connected to internal descriptor controller block and it should be 64bit)

• We can configure BAR0 for transactions as existed, if we disable the internal descriptor option( by configuring BAR0 – 32BIT Non prefetchable and BAR4 – 64 BIT Prefetchable)

Need clarification on descriptor controller part, for transactions from PCIe to any external devices.

Without enabling this internal descriptor can we do normal RD/WR operations?

Is it any external descriptor logic is required if we disabled internal descriptor?

[Rahul_S_Intel1]

May I confirm, the device is Arria10

[Rahul_S_Intel1]

I also assume, you are using Avalon-MM with DMA

[mrama13]

Yes. the device is ARRIA 10 Only

[Rahul_S_Intel1]

Hi ,

 Sorry for the delay in response. Kindly find inline answers 

without enabling this internal descriptor can we do normal RD/WR operations?

>> Yes 

Is it any external descriptor logic is required if we disabled internal descriptor?

>> User can use the with their own logic.

Kindly find the reference for the above. Page no: 15

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-a10-pcie-avmm-dma-16.1.1.pdf