We are wondering whether the 1st block diagram in Fig2 (pg4) "High-Level Block Diagram of Remote System Upgrade" of the following document : 'Remote Update Intel® FPGA IP User Guide'
the FPGA could be compatible to Cyclone V devices because it states 'Passive Serial and Fast Passive Parallel configuration schemes' are supported there at the top of the block diagram compared to the other 2 block diagrams next to it of the same figure.
We are planning to download a new application image remotely from an external host board via I2C to the FPGA (Cyclone V) on our development board (we have no external communication of the host board with the CPLD MAX V). So RSU IP will require to be used inside the Cyclone V FPGA.
Also, seen the following txt within the 'Parallel Flash Loader Intel FPGA IP User Guide'
1.3.6. Using Remote System Upgrade :
"When you instantiate the PFL IP core in the Intel CPLD for FPP or PS configuration, you can use the features in the PFL IP core to perform remote system upgrade. You can download a new configuration image from a remote location, store it in the flash memory device, and direct the PFL IP core to trigger an FPGA reconfiguration to load the new configuration image. You must store each configuration image as a new page in the flash memory device. The PFL IP core supports a maximum of eight pages"
Our project uses CPLD MAX V and it instantiates a PFL IP_core but as stated above the 'Remote Update IP' we were planning to use it within the Cyclone V FPGA. The external on (development) board flash device we use is S29GL01GT, 1Gbit 128Mx8, we are using (targeted flash: CFI parallel 16-bits) FPPx16 configuration scheme.
If the FPGA in the first block diagram listed above of the 'Remote Update Intel® FPGA IP User Guide' & the '1.3.6. Using Remote System Upgrade' of the 'Parallel Flash Loader Intel FPGA IP User Guide' txt above supports Cyclone V for the Remote System Upgrade, why do I get issues with the RSU 'Remote Update IP' not supporting any Passive configuration scheme ?
Reply to this matter will be appreciated.
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