Question about DDR3 mimic path

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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

Question about DDR3 mimic path

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According to ALTMEMPHY manuel, mimic path on Stratix IV memory IP is to compensate the VT variation between the mem_clk and PLL clk.

This design track VT on write path of DDR3 CTRL, but what about the READ path? What if the DQS input drifts away from the calibrated position?:confused:

Anyone give a hint? Thanks a lot.

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