FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6563 Discussions

overflow in video input, how to make it work right?

Altera_Forum
Honored Contributor II
‎04-28-2010 09:21 AM
968 Views

Hi all 

I am using a de2board on which I am trying to make a video processing system. 

My actual problem is that I get an input overflow in cvi. 

I'd like to know HOW can i adjust that. 

I thought that I could use a bigger FIFO, or to speed up system clock, but I think ha ve not enough space on chip. 

I fear that the problem is about the sdram troughput that slows down the video pipeline. 

I am using an SDR SDRAM, 16 bits wide, 100Mhz max controller clock. 

Video system (ips) runs at 100Mhz too. 

any hint please?
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.