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Honored Contributor I
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How to Connect to SOPC Avalong Bus from outside of SOPC

I'm using the SDRAM with Nios and SOPC, but I also need to write to the SDRAM via logic that is outside the SOPC. 

 

How is this typically done? I'm assuming I would need to create a peripheral in sopc that brings out the avalon bus, and then on the top level the logic that wishes to write to the bus (sdram) would need to interface to those signals, but I'm not exactly sure about all the details.  

 

Anyone ever done something like this?
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Honored Contributor I
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Hi, 

 

I have done something like this during the last days. My solution to that problem is as follows: I created an custom Avalon component which has two slave ports, lets call them AV0 and AV1. In this custom component I instantiated the SOPC SDRAM controller. The SDRAM controller is connected with the AV0 port by an multiplexer, and the AV1 slave input serves as an control for this multiplexer. If I send a "connect" instruction to AV1, the SDRAM controller is connected to the Avalon bus of the SOPC system. If I send a "disconnect" instruction to AV1, the SDRAM controller is disconnected from the SOPC Avalon Bus and my custom logic is connected to it. In my particular application, this allows me to write the SDRAM using the NIOS processor and use my custom logic to do a very fast playback of the SDRAM data. 

 

Hope this helps you, 

 

Markus
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Honored Contributor I
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This has been discussed in detail on the forum. I can't find all the posts but here are a few to try: 

 

http://www.alteraforum.com/forum/showthread.php?t=19366&referrerid=2226 

http://www.alteraforum.com/forum/showthread.php?t=12689&referrerid=2226 

 

Jake
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Honored Contributor I
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Markus, I would advise to write your own Avalon master controller instead, and put it along with the SDRAM controller in your SOPC system. SOPC builder will automatically add some arbitration logic, and this solution would be easier to write, test, maintain, and re-use.

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Honored Contributor I
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--- Quote Start ---  

Hi, 

 

I have done something like this during the last days. My solution to that problem is as follows: I created an custom Avalon component which has two slave ports, lets call them AV0 and AV1. In this custom component I instantiated the SOPC SDRAM controller. The SDRAM controller is connected with the AV0 port by an multiplexer, and the AV1 slave input serves as an control for this multiplexer. If I send a "connect" instruction to AV1, the SDRAM controller is connected to the Avalon bus of the SOPC system. If I send a "disconnect" instruction to AV1, the SDRAM controller is disconnected from the SOPC Avalon Bus and my custom logic is connected to it. In my particular application, this allows me to write the SDRAM using the NIOS processor and use my custom logic to do a very fast playback of the SDRAM data. 

 

Hope this helps you, 

 

Markus 

--- Quote End ---  

 

 

Thanks! That does help, and can't wait to try it!  

 

Now here's a dumb question, my system already has an altera sdram controller instantiated in sopc, so if I create a new component that has the mux and controller built in, I should remove the other one (in sopc), correct?
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Honored Contributor I
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--- Quote Start ---  

Markus, I would advise to write your own Avalon master controller instead, and put it along with the SDRAM controller in your SOPC system. SOPC builder will automatically add some arbitration logic, and this solution would be easier to write, test, maintain, and re-use. 

--- Quote End ---  

 

 

 

Just curious, what does the Avalon Master Controller connected to the SDRAM controller get you? Is it easier to interface to the Avalon Master Controller from the outside (user logic) than it is to connect to the avalon bus / SDRAM controller without it? 

 

http://www.alteraforum.com/forum/showthread.php?t=3468 

http://www.altera.com/support/examples/nios2/exm-avalon-mm.html 

http://www.alteraforum.com/forum/showthread.php?t=19053 

http://www.alteraforum.com/forum/showthread.php?t=12689
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Honored Contributor I
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It is easier to create a component with an Avalon master interface if you intend to share the RAM between your custom logic and other components (such as the Nios CPU). I understood from your first post that this is what you wanted to do. 

SOPC builder will automatically create arbitration logic for you to share the RAM, which would be a bit more difficult to do if you had to do it yourself.
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Honored Contributor I
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--- Quote Start ---  

It is easier to create a component with an Avalon master interface if you intend to share the RAM between your custom logic and other components (such as the Nios CPU). I understood from your first post that this is what you wanted to do. 

SOPC builder will automatically create arbitration logic for you to share the RAM, which would be a bit more difficult to do if you had to do it yourself. 

--- Quote End ---  

 

 

Gotcha.. yes that's the goal. 

 

BTW, anyone know how fast I can clock the data in from my user logic to the avalon sopc ram? 

 

All the sopc devices ( cpu, ram, etc) are running off 100mhz.. and my user logic writes 4 bytes every 50mhz. The simple write master is configured for a 256 byte fifo. Unfortunately, when I look at the memory after a second of transfers, it looks bad. It only works when I slow the writes ***WAY**** down. I haven't played with it to see at what speed it starts to go bad, but obviously writing a single 32bit word at speeds anywhere near the avalon sopc speed doesn't work. Anyone else experience such a thing, or have an idea what's going on?
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Honored Contributor I
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SDRAM has a high latency and many clock cycles are necessary before a word can be written or read. 

You can reach Avalon speeds by using bursts, but AFAIK this is only supported by the DDR controller and not the SDR SDRAM.
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Honored Contributor I
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--- Quote Start ---  

SDRAM has a high latency and many clock cycles are necessary before a word can be written or read. 

You can reach Avalon speeds by using bursts, but AFAIK this is only supported by the DDR controller and not the SDR SDRAM. 

--- Quote End ---  

 

 

I did experiment using different memory (on chip ram, sram, sdram), but I couldn't see any difference.., the go strobe always needs to be a fraction of the avalon clock in order for it to work.
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Honored Contributor I
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it should be a lot faster with on chip ram... Is this ram shared with something else?

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Honored Contributor I
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--- Quote Start ---  

it should be a lot faster with on chip ram... Is this ram shared with something else? 

--- Quote End ---  

 

 

Nope, the on-chip 32-bit wide memory is connected only to the master template. I took a snapshot of what I'm seeing..  

 

basically I have a 100Mhz state machine that whenever a 10Mhz data clk goes high, I increment the data, and the address (by 4), and set the data valid/go pulse high (the write length is constant at 4. This addr/data is presented half a clock after dataclock goes high. 

 

At this point these signals to the master template don't change until just before the next data clock.. at which time I deassert go, and wait for the next data clock to present the new data. 

 

When I pause the template/Nios to look at the onchip memory, the transfers are taking place as evident by the incrementing data, however, instead of 1 new value per location, I see new data being written into 6 consecutive addresses. On signaltap I see the addresses correctly incrementing by 4 (32-bit data) and the data incrementing by 1. However the on chip memory is not incrementing by 1 at every address.
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Doh! Its working fine now.. just had to strobe the Go pulse at 100Mhz! 

 

Rather than sampling the level, it would have been nice if the template only does 1 transfer per rising edge..... that way the user logic isn't required to sync to the internal template clock.
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Honored Contributor I
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Just as a heads up I see a common mistake made when users integrate their own memory controllers. Be sure to specify the maximum pending reads properly for your slave port (assuming you support pipelined reads). If you select too low of a value and your slave port doesn't throttle back using waitrequest you will see data dropped. So if you SDRAM supports up to 6 reads in flight then you can set the max pending reads to something like 8. Overestimating this value does no harm to your system besides adding an overkill amount of buffering but underestimating can lead to a functional failure. To give you some examples the SDR SDRAM controller in SOPC Builder uses a max pending reads of 6 or 7 (I forget) and the DDR SDRAM controllers use 16.

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--- Quote Start ---  

To give you some examples the SDR SDRAM controller in SOPC Builder uses a max pending reads of 6 or 7 (I forget) and the DDR SDRAM controllers use 16. 

--- Quote End ---  

 

 

Pardon me for my question..but how do you know about the max pending reads for SDR SDRAM Controller? Is is stated in the setting page of the SDRAM controller or somewhere? I didnt found it..
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Honored Contributor I
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It should be in the controller ptf file. Also it looks like the DDR controllers use 32 now. To find the value I normally open the sopc file in a file editor and search for the slave port.

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