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Valued Contributor III
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Question about RAM IP with registered read and write port

Hi there, I want to generate a 2 port RAM using MegaWizard. 

 

I need that the rdaddress and rdenable inputs without register them first, because this will cause a one clock cycle delay and the internal bus that I use expects that the result shows on the next rising edge of clock when rdaddress and rdenable is high. 

 

I also found that write port has to be registered no matter whether M20K or MLAB is used.  

Read port is different. If I use M20k, I can not choose "no registered" read port. If use MLAB I can. 

 

I wonder is that means I can not use M20K in my situation? 

 

Thanks for any comments!
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Valued Contributor III
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Yes, writing to the RAMs is a clocked event. There is no way around this. Reading from the M20K is also always one clock cycle. Hopefully there is some other way you can design around this.

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Valued Contributor III
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--- Quote Start ---  

Yes, writing to the RAMs is a clocked event. There is no way around this. Reading from the M20K is also always one clock cycle. Hopefully there is some other way you can design around this. 

--- Quote End ---  

 

 

 

Thanks for your comments. 

I actually found one user manual from Altera. One page 4-12, it shows that the read data shows at the very first rising edge of clock cycle.  

However, if it is registered, it should happen at the second rising edge of clock cycle, since the first rising edge is to fill the input register.  

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_ram.pdf 

 

Is the manual incorrect here?
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Valued Contributor III
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Valued Contributor III
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You can read in one clock cycle on M20K. There is an optional output register which brings it up to two cycles, and is necessary for high speed designs to meet timing. (High speed being a lose term, very dependent on your device, speed grade and frequency requirement)

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Valued Contributor III
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--- Quote Start ---  

You can read in one clock cycle on M20K. There is an optional output register which brings it up to two cycles, and is necessary for high speed designs to meet timing. (High speed being a lose term, very dependent on your device, speed grade and frequency requirement) 

--- Quote End ---  

 

 

 

Can I assume that there is still a register for the input ports, after the first clock cycle, the value and enable will be registered. If take memory similar as a "combinational logic", it will show the data once there is address and read enable. The desired value will be at the output port.  

And also if using output buffer as you said, there will be two clock cycle. 

 

So I can understand memory like that?  

 

Thanks!
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Valued Contributor III
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Yes, that sounds right. Once you start simulating the block it's in, you'll quickly confirm.

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Valued Contributor III
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--- Quote Start ---  

Yes, that sounds right. Once you start simulating the block it's in, you'll quickly confirm. 

--- Quote End ---  

 

 

Thanks Rysc! I appreciate it very much!
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