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PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Efficient DDR3 usage in video application on Cyclone V

Honored Contributor II

I have 16bit DDR3 on my custom board. Now I'm using hard memory IP DDR3 SDRAM Controller with UniPHY with full rate on Avalon MM interface(330MHz). All local ports on controller are 32bit width data bus. I enabled AFI half rate clock in contoller settings. All MM masters (Frame_Reader, Frame_Buffer) have also 32bit data bus, and its operate on AFI half rate clock.  



But now I investigate CVGT_VIP_Exmple from Altera, and I see soft memory controller using here on half rate on Avalon MM interface. Port have 128 bit data width (external memory have 32 bit data). So why hard memory controller is not using in this example? I assume hard memory IP shuld be more productive. What is more efficien in video application - hard contoller on a full rate, or soft contoller on half rate?
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