Question about UniPHY with DDR2

[XQSHEN]

1) avl_size only has 3 bits, how to set burstcount = 8?

2) during ddr2 simulation using intel model, there are two many avl_ready = 0 even I set avl_size = 3'd4;

It significantly impact the data transfer efficiency. How to improve it?

[ybin · Accepted solution]

Hello,

avl_size is generated according to the maximum AVMM burst length, the default length is 4, this is why you will find the signal is only 3bits. You can enlarge burst length is you want to improve efficiency of controller.

[XQSHEN]

Should that setting impact the burst length of below?

[ybin]

The setting you mentioned doesn't impact avl_size, but it can impact efficiency, the default value is 8, no need to modify it. You can just modify maximum AVMM burst length value.

[XQSHEN]

Thanks, it's clear now. You can close this topic.

[ybin]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.