I've been asked to compare time domain vs. frequency domain processing for a particular algorithm in terms of FPGA resource usage.
Essentially, I'm looking at logic resource usage to implement an FFT followed by a multiply followed by an inverse FFT compared to a convolution with n-weights in the time domain (or basically an FIR with n coefficients). I'm pretty clear on usage going the FFT route but I'm not so clear on how to interpret the resource usage table in the FIR II IP Core user guide. I expect to see information in the table that would help me estimate the FPGA resource usage for an FIR implementation with n-coefficients. Could someone explain the resource usage table? In particular, the parameters section. What do the Channel, Wires, and Coefficients columns represent? FIR II IP User Guide here: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_fir_compiler_ii.pdfhttp://www.alteraforum.com/forum/attachment.php?attachmentid=10898&stc=1 Thanks