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Modelsim 10.1 PE syntax error for "tse_10_100_1000_mac" IP core

Altera_Forum
Honored Contributor II
1,216 Views

Hi, 

 

I have used "tse_10_100_1000_mac" IP core in my design While verifying the design I compiled the tse_10_100_1000_mac IP core to proceed further with verification activity. But modelsim 10.1 PE is reporting syntax error stating 

"** Error : ../../design/ altera_tse_top_gen_host.v (1) : Syntax error, unexpected non-printable character 0x8b 

** Error : ../../design/ altera_tse_top_gen_host.v (1) :Syntax error, unexpected $undefined , expecting class" 

 

As it is IP , its files are encrypted and I could not view design file to fix the issue,  

Kindly let me know how to resolve this issue.  

 

Additional Info : 

Quartus -II 64 bit V13.1.0 

ModelSim PE 10.1c 

 

Looking forward for solution. 

 

Thank you for your valuable time in reading thread.
0 Kudos
7 Replies
Altera_Forum
Honored Contributor II
122 Views

If the simulation model does not exist, the error messages may be issued. Did you use the auto-generated msim_setup.tcl to compile simulation libraries?

Altera_Forum
Honored Contributor II
122 Views

Hi kkaibara, 

 

Thanks for your time,  

I am using my own script to run simulation,I coded it using vsim commands. Apart from this I am using verilog design files of "tse_10_100_1000_mac" taken from IP core directory, files are as mentioned below , 

1. altera_tse_reset_synchronizer.v (file size : 3 Kb) 

2. altera_tse_top_gen_host.v (syntax error in this file- Encrypted file, Size : 62 Kb)  

3. altera_tse_mac.v (file size : 18 Kb) 

 

Thanks  

N.R.M
Altera_Forum
Honored Contributor II
122 Views

What I did is loading msim_setup.tcl in my custom script like below. 

 

# Triple Speed Ethernet MAC 

source ./../altera_tse_sim/mentor/msim_setup.tcl 

set QSYS_SIMDIR "./../altera_tse_sim/" 

set QUARTUS_INSTALL_DIR "c:/altera/13.1/quartus/" 

# Compile device library files 

dev_com 

# Compile the design files in correct order 

com 

 

Where altera_tse is the name of my TSE IP, altera_tse_sim is the silumation lib folder Quartus II software generated. QSYS_SIMDIR and QUARTUS_INSTALL_DIR parameters are used in the msim_setup.tcl. 

 

I have learnt this way from the TSE's testbench. I like that.
Altera_Forum
Honored Contributor II
122 Views

From your post I could understand that you were trying to simulate TSE's test bench. But I have written design in VHDL and TSE Ip core design files are in verilog, which i compiled successfully except  

altera_tse_top_gen_host.v (syntax error in this file- Encrypted file, Size : 62 Kb) 

 

 

I am sharing my batch_run.bat , hoping you will get better clarity on the issue, 

 

vlib work 

vlib design 

vmap work design 

vcom -work design -f lib.dgn 

vcom -work work -f lib.dgn 

vlog -work work ../../design/altera_tse_reset_synchronizer.v 

vlog -work work ../../design/altera_tse_top_gen_host.v 

vlog -work work ../../design/altera_tse_mac.v 

vcom -2008 -work work -f rtl.dgn 

vcom -2008 -work work -f tb.dgn 

vcom -2008 -work work ../tests/IF_FPGA_TS.vhd 

vsim work.IF_FPGA_TB -l IF_FPGA_TEST.log -do msim.do -c -quiet -t 1ps 

move IF_FPGA_TEST.log ../logs/IF_FPGA_TEST.log 

move vsim.wlf ../waves/IF_FPGA_TEST.wlf 

 

 

After running this script compiler is reporting the error. 

** Error : ../../design/ altera_tse_top_gen_host.v (1) : Syntax error, unexpected non-printable character 0x8b 

** Error : ../../design/ altera_tse_top_gen_host.v (1) :Syntax error, unexpected $undefined , expecting class 

 

 

I have directly copied TSE's design files from quartus TSE directory to my design folder.
Altera_Forum
Honored Contributor II
122 Views

You must compile all files listed in the msim_setup.tcl to run your custom testbench. They are not only for the TSE’s testbench. This is because altera_tse_mac.v calls many sub-modules in *_sim folder and device specific primitives in Quartus II install folders. You can find the file list in the msim_setup.tcl and can copy them to your script. But the easiest way is calling the msim_setup.tcl in your script as I described before. 

 

If I run your testbench, and if the target device is Arria V, I will do this. 

 

vlib work 

vlib design 

vmap work design 

vcom -work design -f lib.dgn 

vcom -work work -f lib.dgn 

# vlog -work work ../../design/altera_tse_reset_synchronizer.v 

# vlog -work work ../../design/altera_tse_top_gen_host.v 

# vlog -work work ../../design/altera_tse_mac.v 

 

# Triple Speed Ethernet MAC 

source ./../altera_tse_sim/mentor/msim_setup.tcl 

set QSYS_SIMDIR "./../altera_tse_sim/" 

set QUARTUS_INSTALL_DIR "c:/altera/13.1/quartus/" 

# Compile device library files 

dev_com 

# Compile the design files in correct order 

com 

 

vcom -2008 -work work -f rtl.dgn 

vcom -2008 -work work -f tb.dgn 

vcom -2008 -work work ../tests/IF_FPGA_TS.vhd 

# vsim work.IF_FPGA_TB -l IF_FPGA_TEST.log -do msim.do -c -quiet -t 1ps 

 

vsim -L work -L work_lib -L i_tse_mac -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L arriav_ver -L arriav_hssi_ver -L arriav_pcie_hip_ver work.IF_FPGA_TB -l IF_FPGA_TEST.log -do msim.do -c -quiet -t 1ps 

 

move IF_FPGA_TEST.log ../logs/IF_FPGA_TEST.log 

move vsim.wlf ../waves/IF_FPGA_TEST.wlf 

 

Please remember necessary files must be placed in proper folders the msim_setup.tcl refers to.
Altera_Forum
Honored Contributor II
122 Views

Thank you kkaibara , I will check it.

Altera_Forum
Honored Contributor II
122 Views

Hi kkaibara,  

 

I am using my own "run.do" file as below (snippet) 

 

set ETH_DIR "../TSE_10_100_1000_MAC" 

vlog -work work ${ETH_LIB}/altera_tse_reset_synchronizer.v 

vlog -work work ${ETH_LIB}/altera_tse_top_gen_host.v 

vlog -work work ${ETH_LIB}/altera_tse_mac.v 

vcom -work work ${ETH_DIR}/tse_10_100_1000_mac.vhd
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