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Altera_Forum
Honored Contributor I
1,026 Views

Questions about SGDMA's IN connected to Avalon-ST Dual Clock FIFO.

If SGDMA(Stream to Memory)'s IN is connected to Avalon-ST Dual Clock FIFO's out,the there are SOP,EOP signals built in SGDMA IN port. 

The SOP,EOP inside SGDMA IN port is INPUT attributes,and the DC FIFO's out's SOP,EOP is OUTPUT. 

 

There is just avalon-st signals,if a sgdma reads,such as 12 bytes data,from the dc FIFO. 

how does the fifo knows how many data will be read and when to change its SOP/EOP signal?
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6 Replies
Altera_Forum
Honored Contributor I
63 Views

The Fifo also has SOP/EOP signals on it's inputs and will transmit them at the same time than the data. The packet size on the output will be the same than the one on the input.

Altera_Forum
Honored Contributor I
63 Views

Thank you Xiwen! 

Sorry for I'm a greenhand in FPGA,I still have some questions. 

 

You mean that the SOP/EOP in the INPUT port of DC_FIFO will be sent to OUTPUT port of DC_FIFO at the same time transparently without any change? 

 

So, 

If DC_FIFO receeives a data with its packet size is 0x2000 for example,and SGDMA reads 512 bytes data from DC_FIFO to send to PCIe IP each time. 

The SGDMA just reads 512 bytes data from DC_FIFO as when the SOP of DC_FIFO is high and EOP of DC_FIFO is low,and when the reading operation is end, 

I mean that SGDMA have read 512 bytes data,the SGDMA can end the operation by itself,and do NOT have to wait EOP signal is HIGH? 

 

Best Regards~
Altera_Forum
Honored Contributor I
63 Views

I'm sorry I don't understand your question. A packet size of 0x2000 is more than 512 bytes. The SOP and EOP signals just signal the start and end of a packet. When the DC_FIFO receives a packet , its start will be signaled by a SOP high, and its end by a EOP high. The DC_FIFO will just reproduce the same behaviour on it's output, asserting the SGDMA's SOP output at the start of packet and EOP at its end. If you configure the SGDMA to use the EOP signal (i.e. set the transfer length to 0 bytes) then it will read data coming from the DC_FIFO until it sees the EOP signal asserted.

Altera_Forum
Honored Contributor I
63 Views

Thanks Daixiwen. 

"If you configure the SGDMA to use the EOP signal (i.e. set the transfer length to 0 bytes) then it will read data coming from the DC_FIFO until it sees the EOP signal asserted." 

Or else the SGDMA will receive data accroding to the descriptor and ignore the EOP signal?
Altera_Forum
Honored Contributor I
63 Views

Yes if you set a specific length, the DMA will read that amount of data, ignoring the EOP signal.

Altera_Forum
Honored Contributor I
63 Views

i think I understand.Thank you very much.

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