FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

Altera DMA Issue

Cannot resolve algebric loop

A problem with runing the alt_dspbuilder_createComponentLibrary

Reed-Solomon decoder parameters

Need help to make Triple Speed Mac's avalon-MM interface work.

How do I create AXI3 interface to DDR3 SDRAM Controller with UniPHY?

Simple data transfer over PCIe for co-processing

Pcie Address problems

AltPll Dynamic phase shift state machine

Need some advices on designing multiple DMA in a PCIE bridge chip

PCI Express - chaining DMA - newbie Q

Modular SGDMA

TSE + Custom PCB w/Vitesse VSC8601

In 100G MAC+PHY simulation tx5l_ack signal sometimes goes to zero

Complex Coefficients with FIR Compiler II

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How to chose our PCIe implemenation solutions, Avalon-MM or Avalon-ST?

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