Questions regarding Linux driver in $QUARTUS_ROOT/ip/altera/altera_pcie/altera_pcie_software

[zener]

In Quartus there is source code for a pcie device driver in $QUARTUS_ROOT/ip/altera/altera_pcie/altera_pcie_software. 

1) Which example design is compatible with this device driver?

Since the driver appears to set up DMA descriptors they should match the ones in the RTL. But which sample design or IP is compatible with this device driver?

2) How should the file intel_fpga_pcie_ip_params.h.terp be pre-processed?

In $QUARTUS_ROOT/ip/altera/altera_pcie/altera_pcie_software/kernel there is a file named intel_fpga_pcie_ip_params.h.terp which appears to be pre-processed by some Tcl based tool which defines the list $bar_types, dma_interrupt_enabled and dma_interrupt_type. The pre-processed file is included by intel_fpga_pcie_setup.h, which is included by the C source files.

How is this supposed to be done?

3) It does not compile under Linux 5.x kernel, but it should be possible to port by updating some function arguments etc.

Did anybody already port $QUARTUS_ROOT/ip/altera/altera_pcie/altera_pcie_software/kernel/linux to the 5.x kernel?

[wchiah]

Hi,

1. The device driver in $QUARTUS_ROOT/ip/altera/altera_pcie/altera_pcie_software is designed to be compatible with the Altera PCIe IP core. The example design provided with the Intel PCIe IP core. Can I know where you get the file location ? it shall compatible with the example design that you generated.
2. The file intel_fpga_pcie_ip_params.h.terp is likely to be processed by the Tcl Preprocessor (terp), which is a tool used to preprocess Tcl scripts. To process this file, you can run the command:
   1. terp intel_fpga_pcie_ip_params.h.terp > intel_fpga_pcie_ip_params.h
   2. This command will generate the pre-processed file intel_fpga_pcie_ip_params.h, which will then be included by the other source files. The Tcl Preprocessor tool is typically included with the Altera Quartus Prime software suite.
3. I do not have information on whether someone has already ported the device driver located at $QUARTUS_ROOT/ip/altera/altera_pcie/altera_pcie_software/kernel/linux to the Linux 5.x kernel. This may be a task that requires changes to the source code to ensure compatibility with the new kernel version, as mentioned in your statement "it should be possible to port by updating some function arguments etc." It is possible that the OpenSource community may have information on a pre-existing port, but it may also require effort to port the code yourself.

Hope that answer your question.

Regards,

Wincent_Intel

[zener]

Thank you for your reply.

1) Which example design does the device driver go with, ep_g1x1_APPS (included in the IP catalog) or the more generic one?
The latter is found in: $QUARTUS_ROOT/ip/altera/altera_pcie/altera_pcie_a10_ed

2) There is no file named terp in my Quartus installation:
find v21.3.0.170_pro/ -name terp -type f

Gives no output. I can find some tcl libraries related to terp, but no script/program named terp.

3) I've done some updates to support 5.x kernel changes, e.g. the changed access_ok parameters. But there seem to be a global variable which is not defined. It's declared as extern in:

intel_fpga_pcie_setup.h:extern struct global_bookkeep global_bk;

But I can't find the actual global anywhere. Did anybody manage to compile it on a 3.10.514 system?

[wchiah]

Hi,

Please accept my apology for late reply.
Can I know the reason you trying to look at the $QUARTUS_ROOT/ip/altera/altera_pcie/altera_pcie_a10_ed file ?

Is there any objective of doing it ? I am thinking is there any alternative/better way to perform what you trying to achieve.

Regards,

Wincent_Intel

[zener]

Thank you. I'm basically looking for a Cyclone 10GX PCIe reference design and a Linux driver/sw to write/read data from/to the host CPU to the FPGA RAM.
First I tried to find a simple PIO based design to do this as I asked in this thread:

https://community.intel.com/t5/Programmable-Devices/Cyclone-10GX-dev-kit-PCIe-simple-PIO-example-using-Linux-host/m-p/1435380#M88097

As I was not able to find a simple PIO reference design/driver/sw I was going for the the somewhat more complex version using DMA.

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[wchiah]

Hi,

Thanks for sharing with me, If you are looking at PIO reference design, you may consider F-tile Agilex device

https://www.intel.com/content/www/us/en/docs/programmable/683372/22-4-8-0-0/running-the-pio-design-example.html

above link shows some related information about the design. Hope this is helpful.

Regards,

Wei Chuan

[wchiah]

Hi,

I wish to follow up with you about this case.

Is it answering your question ? let me know if I can help more

Regards,

Wincent_Intel

[wchiah]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

Regards,

Wincent_Intel

[wchiah]

Hi

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

Regards,

Wincent_Intel