RLDRAM II in Stratix IV

FPGA Intellectual Property

PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

RLDRAM II in Stratix IV

1,016 Views

Hi, everyone,

I have a question about rldram ii controller in Stratix IV.

Now, our device connect two rldram ii on the single board, I generated two rldram ii ip core in the device, but only one can normally run, another even caliburation fail and can`t initial down.

But, when I separately gen one core in the device to test the memory on the board, they all can work.:confused:

I didn`t share the pll/dll, and used itselves constraint files.

If someone knows something about it, please help me :)

Link Copied

0 Replies

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.