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Altera_Forum
Honored Contributor I
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RLDRAM II in Stratix IV

Hi, everyone, 

 

I have a question about rldram ii controller in Stratix IV. 

 

Now, our device connect two rldram ii on the single board, I generated two rldram ii ip core in the device, but only one can normally run, another even caliburation fail and can`t initial down. 

 

But, when I separately gen one core in the device to test the memory on the board, they all can work.:confused: 

 

I didn`t share the pll/dll, and used itselves constraint files. 

 

If someone knows something about it, please help me :)
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