Ram memory read 2 cycle delay

[Altera_Forum]

I use Memory compiler in MeagWizard to generate 1-port Ram. 

 but there are both one register at input and output, this make read delay 2 cycle.  I want to know if there is anyway to make Ram read delay only one cycle  just like ASIC memory or something did I miss ?  device: cyclone V E (DE0)  software: 11.1sp2

[Altera_Forum]

On the latter pages, there should be option to disable registered outputs.

[Altera_Forum]

--- Quote Start ---  On the latter pages, there should be option to disable registered outputs.  --- Quote End ---    omg haha thanks  I knew that I must be missing something :p