HelloI am designing a custom controller for LPDDR2 devices and i prefered using the ALTERA's uniPHY in an ARRIA-V device. I have allready designed the controller up to the "afi-3.0" bus and connected a uniPHY that i generated using the QuartusII 12.0 - Megawizard. I am also using micron's model for the memory device. I have simulated write and read cycles following the minimal initialization sequence that the uniPhy performed. The write cycle is perfect. During the following read cycle from the same address, i can see the model delivering the data back to the uniPHY. The uniPhy asserts the "afi_rddata_valid" signal but leaves zeroes on the "afi_rdata" bus. I had thoughts that maybe the uniPHy is missing the data from the memory model, so i initiated a very long write & read burst, assuming some of the burst will be caught, but the "afi_rdata" is still all zeroes. Any thoughts? Does anybody have an experience like that using uniPhy with any kind of DDR device? Thanks
I know this was ages ago but for anyone else out there that comes across thisCheck that you are controlling the afi_rdata_en and afi_rdata_en_full. If you miss out 1 of them you get all zeros coming from the Uniphy yet it will behave normally in functional simulation
I've seen the same thing on the first read. A subsequent read is ok. Uniphy (quartus 13.1, stratixiii, ddr2) doesn't bring out the signals afi_rdata_en or afi_rdata_en_full so I'm not sure how I'd control them.
The afi_rdata_en and afi_rdata_en_full appear for me when I use just Uniphy. I use my own controller not the Altera controller. If they are not there on the top level then you probably don't need to control them. Your problem sounds different to what I reported. Check the timing of your signals match exactly what is in the EMi handbook for your setup. You can also simulate the example design that is generated from the megafunction generation. Look at how it controls the signals.