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Reading from On-Chip FIFO does not consumes data

quir_ol
Beginner
1,380 Views

Hello all,

 

Im trying to read data from On-Chip FIFO. The problem I have is that it seems that the FIFO does not 'advance' whenever I read a new data. What I mean is, I'm able to read the FIFO's level and one value, however after this, the FIFO's level remains the same, and if I read again the same value is returned.

How can I acheive the FIFO to return new data each time I read?

 

Im using altera_avalon_fifo_init() to initialize as follows:

~~~

altera_avalon_fifo_init( MY_FIFO_CSR_BASE,  0x0, 1,  ( MY_FIFO_FIFO_DEPTH-10));

~~~

 

For reading a value im using:

~~~

int first_in_fifo_data = altera_avalon_fifo_read_fifo( MY_FIFO_CSR_BASE,  MY_FIFO_BASE);

~~~

 

The corresponding FIFO's definitons in system.h are following:

~~~

#define MY_FIFO_AVALONMM_AVALONMM_DATA_WIDTH 32
#define MY_FIFO_AVALONMM_AVALONST_DATA_WIDTH 32
#define MY_FIFO_BASE 0xc0
#define MY_FIFO_BITS_PER_SYMBOL 32
#define MY_FIFO_CHANNEL_WIDTH 0
#define MY_FIFO_ERROR_WIDTH 0
#define MY_FIFO_FIFO_DEPTH 256
#define MY_FIFO_IRQ -1
#define MY_FIFO_IRQ_INTERRUPT_CONTROLLER_ID -1
#define MY_FIFO_NAME "/dev/MY_FIFO"
#define MY_FIFO_SINGLE_CLOCK_MODE 0
#define MY_FIFO_SPAN 8
#define MY_FIFO_SYMBOLS_PER_BEAT 1
#define MY_FIFO_TYPE "altera_avalon_fifo"
#define MY_FIFO_USE_AVALONMM_READ_SLAVE 1
#define MY_FIFO_USE_AVALONMM_WRITE_SLAVE 0
#define MY_FIFO_USE_AVALONST_SINK 1
#define MY_FIFO_USE_AVALONST_SOURCE 0
#define MY_FIFO_USE_BACKPRESSURE 1
#define MY_FIFO_USE_IRQ 0
#define MY_FIFO_USE_PACKET 0
#define MY_FIFO_USE_READ_CONTROL 1
#define MY_FIFO_USE_REGISTER 0
#define MY_FIFO_USE_WRITE_CONTROL 0

~~~

 

 

 

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sstrell
Honored Contributor III
1,272 Views

According to this, you've got your addresses swapped in your read command:

https://www.intel.com/content/www/us/en/docs/programmable/683130/22-3/altera-avalon-fifo-read-fifo.html

The FIFO output (the agent interface) should be listed first and the CSR interface should be listed second.

View solution in original post

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8 Replies
sstrell
Honored Contributor III
1,361 Views

So how did you implement this FIFO?  Is it a standalone IP you created from the IP Catalog (show screenshot of parameter settings) or is this in a Platform Designer system?  And are you writing code for Nios or bare metal code for an HPS?  More info needed about the actual hardware implementation here.

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SyafieqS
Employee
1,351 Views

Seem like you are embedded code for FIFO. Is this from Intel IP or custom IP?

Does the functionality works as expected? More info needed here.


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SyafieqS
Employee
1,314 Views

May I know if there is any update from previous reply?


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quir_ol
Beginner
1,292 Views

Thanks you all for the replys!

 

The FIFO is from Intel (added from the Platform Designer System). And the code I'm writing is for the NiosII. Here some details:

 

quir_ol_0-1664873174087.png

 

quir_ol_1-1664873174095.png

 

 

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quir_ol
Beginner
1,282 Views

I guess I'm missing some important details about the functionality of this FIFO of NiosII.  For me as a client, what I understand of a FIFO is: I will read a value from the fifo (the oldest that arrived to the FIFO), and under the table the FIFO will pop that value, and advance to next available value. Me as a client wont care about, checking is there is a new value to point to, advancing the write/read head of the FIFO, handling cases like trying to write when the FIFO is full, etc.

Or in this case, should all this be handled by the client by software? (In that case whats the FIFO here, just an array?)

 

On the other hand, do you know any code examples avilable on how to reading/writing data to FIFOs by software on the NiosII? The only example I have found is for the initialization (https://www.intel.com/content/www/us/en/docs/programmable/683130/22-1/software-example.html).

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sstrell
Honored Contributor III
1,273 Views

According to this, you've got your addresses swapped in your read command:

https://www.intel.com/content/www/us/en/docs/programmable/683130/22-3/altera-avalon-fifo-read-fifo.html

The FIFO output (the agent interface) should be listed first and the CSR interface should be listed second.

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quir_ol
Beginner
1,261 Views

This solve the issue! Thanks for the reply.

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SyafieqS
Employee
1,196 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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