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ESama
Beginner
299 Views

Ref Clock problem in the simple_socket_server exemple based on the Triple Speed Ethernet for Cyclone 10 GX Development kit through Quartus 18.1

Hello

 

I get the following error when I try to compile with quartus 18.1 the simple_socket_server exemple given for the Cyclone 10 GX dev kit :

 

"Error(18694): The reference clock on PLL "sss_qsys_inst|tse_0_tse|tse_mac|i_lvdsio_rx_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification. "

 

The dev kit uses the same 2A bank for both the pcs_ref_clk signal and the SGMII signals and the pcs_ref_clk signal is connected to a dedicated clock input that should be well suited for that purpose.

  • How can I solve this problem (with quartus 18.1) ?
  • If the problem is coming from the actual design of the cyclone 10GX dev kit card, what would be the best choice for the pcs_ref_clk pin and for the SGMII pins (for a new PCB development) ?

Very best regards

Happy new year !

Etienne

 

0 Kudos
8 Replies
Deshi_Intel
Moderator
100 Views

HI,

 

You can refer to below link for the solution.

 

Thanks.

 

Regards,

dlim

 

Nikolay_Rognlien
New Contributor I
100 Views

Hi.

 

The link you provided is broken...

Do you have an updated link that works? I would like to see it...

 

Thanks

Nikolay

 

ESama
Beginner
100 Views

Hello Nikolay Please find below a new link to the zip file. https://we.tl/t-P3EMrZrg3x The original request were: Triple Speed Ethernet : Low data rate with Simple Socket Server exemple I 'm using the simple_socker_server exemple proposed with the Cyclone 10GX dev kit. The FPGA card is connected to a PC through a 1 Gbps Ethernet link. The exemple is working well with out any PB. In order to evaluate the data rate performance, I added in the SSSSimpleSocketServerTask a loop to transmit 10 000 time a buffer of 1 ko with the send() function. The transfer takes 8 s to be completed. By replacing the FPGA dev kit by a socket server implemented in a PC through the same 1 Gbps Ethernet link, the transfer takes roughly 0.2 s. Where does the problem com from ? Thank you for your help Best regards Etienne Samain SigmaWorks Le 18/02/2020 à 14:07, Intel Forums a écrit :
Deshi_Intel
Moderator
100 Views

HI Nokolay,

 

Yup, looks like the KDB link is broken. You can refer to attached pic for KDB detail first.

 

I will feedback to Intel IT to fix the link.

 

Thanks.

 

Regards,

dlim

Deshi_Intel
Moderator
100 Views

HI Nokolay,

 

The broken KDB link is now fixed.

 

Thanks.

 

Regards,

dlim

ESama
Beginner
100 Views

OK, Thanks

Best regards

Deshi_Intel
Moderator
100 Views

welcome !

Deshi_Intel
Moderator
100 Views

Hi,

 

Hopefully the KDB link works for you and clear your doubt.

 

For now, I am setting this long idle case to closure.

 

Thanks.

 

Regards,

Deshi

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