I get the following error when I try to compile with quartus 18.1 the simple_socket_server exemple given for the Cyclone 10 GX dev kit :
"Error(18694): The reference clock on PLL "sss_qsys_inst|tse_0_tse|tse_mac|i_lvdsio_rx_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification. "
The dev kit uses the same 2A bank for both the pcs_ref_clk signal and the SGMII signals and the pcs_ref_clk signal is connected to a dedicated clock input that should be well suited for that purpose.
Very best regards
Happy new year !
Yup, looks like the KDB link is broken. You can refer to attached pic for KDB detail first.
I will feedback to Intel IT to fix the link.