On our Board we are using Cyclone V GX FPGA with Intel/Altera DisplayPort IP (Version 15.1, used as source, 2 lanes , 2.7 Gbps), connected to a NXP DisplayPort to LVDS Bridge PTN3460IBS. This constellation is working fine in hundreds of our devices. But sometimes it happens that the link Training is failing. In the attachment there is a log file with the AUX debug traces in the failing case. It can be seen that the link training is beginning correctly. Then the IP is sending the command
[SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 00
forever and the sink is answering correctly each time.
The DisplayPort IP core seems to be hanged up.
Is this bug known? How could it be fixed?
It's not easy to debug link training log without the decoder.
From your link training failure log file, it's hard to tell whether this is link training failure issue or link training stuck issue.
It's tough to isolate whether the issue is with DP source chip, DP sink chip or the board connection design itself.
Some debug proposal as below.
I have not hear back from you for 2 months. Hopefully my debug suggestion help out and you are able to make progress with your project.
For now, I am setting this case to closure.