FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6059 Discussions

Reference Design RP to EP?

Zarquin
Novice
210 Views

Dear Community,


I am looking for a small, well-explained example or tutorial for a very simple data transfer between a PCIe SOC HIP Root Port and an PCIe HIP endpoint.

 

I worked through this: https://rocketboards.org/foswiki/Projects/PCIeRootPort

and that: https://rocketboards.org/foswiki/Projects/PCIeRootPortWithMSI

But there are files missing and errors occur and the projects are not well enough documented to find the errors without too much effort.

 

My Dev Kits are:

 

Best Regards

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5 Replies
EBERLAZARE_I_Intel
182 Views

Hi,


Can you check from your side if you can access the full design here:

https://releases.rocketboards.org/release/2015.10/pcie-ed/hw/




EBERLAZARE_I_Intel
166 Views

Hi,


Do you have any update?


Zarquin
Novice
159 Views

 

Dear EBERLAZARE,

I can access the full design files from your link above.

But these seem to be the hardware files from the Rocket PCIe RootPort with MSI example I already have. (?)

The problem with the Rocket examples is that the:

I tried to combine the examples but without success.

 

Best regards

 

EBERLAZARE_I_Intel
144 Views

Hi,


Unfortunately, you may have to build the Uboot and kernel after compiling the GHRD in Quartus, as demonstrate at the bottom of the page.




EBERLAZARE_I_Intel
126 Views

Hi,


Do you have any further questions?


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