FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6356 Discussions

Regarding IP core H/W tcl file

Altera_Forum
Honored Contributor II
‎04-06-2010 12:23 PM
1,249 Views

Hi All, 

 

I am tring to design SOPC componet with 2 Avalon Memory Mapped Slave Interfaces with two seprate clock so is it possible to create such type of componet? 

 

Thamks in advance 

 

Regards 

dg
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Altera_Forum
Honored Contributor II
‎04-06-2010 01:23 PM
206 Views

Yes, this is achievable. 

 

create 2 clock interface and 2 slave interface. 

Associate 1 clock for each slave.
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Altera_Forum
Honored Contributor II
‎04-07-2010 08:15 AM
206 Views

hi, 

 

thnks a lot with this i got the solution of my problem...!! 

 

 

Rgds 

DG
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