FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
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Regarding building a Qsys component.

Honored Contributor II

Hello, I am new to fpga programming and i am stuck at a point while converting my Verilog HDL code into a Qsys/SOPC component. 

The verilog description is an interface for P30 flash on Cyclone III board which implements March Algorithm to test the flash memory. It starts the test when switch is pressed.  

I want make an SOPC/Qsys component to implement the same but can be incorporated in any design such that when the switch is pushed, SOPC system aborts it normal functionality and enters the flash test mode. 


I am confused about how to send the interrupt to bring the SOPC system into test mode when switch is pressed.
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