Decided to raise another ticket wrt this matter. Can please someone reply to this one
I looked at the Remote Update IP and when I select MT25QU01G as the configuration device, I also enabled all 3 following options :
Add support for writing configuration parameters
Add support for Avalon interface
Enable recording POF checking
The avi_csr_writedata (in) and avi_csr_readdata (out) ports are 32bit wide & address shown in the block symbol asmi_addr (out) is 32bits wide too.
With MT25QU01G as the configuration device, if we write to avi_csr_writedata a 32 bit value can we then read the 32 bit value out of avi_csr_readdata as parallel data in just one clock cycle if eg the address used to write and read is at offset 0x3 (Register RU_PAGE_SELECT) to avl_csr_address(2:0) with a value of 0 ?
Register RU_PAGE_SELECT in reality will represent reading or writing the start address of configuration
image. So if we read out the 32bits value in 1 clock cycle we will NOT require to use a S2P converter at the output of the 'Remote Update Intel IP' data/addr lines and connect it directly to the parallel PFL.
We are planning to just use 16 low bits (15:0) of data and 26 low bits (25:0) of address to connect to out parallel flash x16 corresponding data/addr lines.
Is my assumption here is correct ie S2P conversion will not be required if we get parallel data coming out of the Remote Update IP with the MT25QU01G selected as the configuration device?
We realised that this is thread is a duplicated thread of 04980343. I am now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.