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Honored Contributor I
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SCFIFO simulation stucks

The following testbench stucks if SCFIFO has these parameters: 

.USE_PACKETS (1 ), .USE_STORE_FORWARD (1 ), .EMPTY_LATENCY (1 ), .USE_MEMORY_BLOCKS (1 )  

It works fine if EMPTY_LATENCY is 3.  

I haven't seen any notifications that it is forbidden to use EMPTY_LATENCY = 1 in this case. Did I miss something? 

 

`timescale 1 ns / 1 ns module tb_scfifo_2; localparam CLK_PRD = 10; localparam N_CH = 1; logic i_clk; logic i_rst; logic in_data ; logic in_valid ; logic in_startofpacket ; logic in_endofpacket ; logic in_empty ; logic in_error ; logic in_ready ; logic out_data ; logic out_valid ; logic out_startofpacket ; logic out_endofpacket ; logic out_empty ; logic out_error ; logic out_ready ; logic csr_address ; logic csr_write ; logic csr_read ; logic csr_writedata ; logic csr_readdata ; logic almost_full_data ; logic almost_empty_data ; int unsigned seed = 20; /////////////////////////////////////////////////////////////////// // Test /////////////////////////////////////////////////////////////////// // Clock initial begin i_clk = 1'b1; forever# (CLK_PRD / 2) i_clk = ~i_clk; end // Reset initial begin i_rst = 1'b1; # (CLK_PRD * 3 + 1) i_rst = 1'b0; end // Main sequence initial begin // Init signals in_data = 1'b0; in_valid = 1'b0; in_startofpacket = 1'b0; in_endofpacket = 1'b0; in_empty = 1'b0; in_error = 1'b0; csr_address = 1'b0; csr_write = 1'b0; csr_read = 1'b0; csr_writedata = 1'b0; out_ready = 1'b1; $timeformat(-9, 3, " ns", 10); // Test sequence # 1; # (CLK_PRD * 10); for (int i = 0; i < 100; ++i) begin // SOP in_valid = 1'b1; in_startofpacket = 1'b1; in_data = unsigned'($random(seed)); in_data = unsigned'($random(seed)); # CLK_PRD; in_startofpacket = 1'b0; # (CLK_PRD * 3); // EOP in_endofpacket = 1'b1; # CLK_PRD; // End in_valid = 1'b0; in_endofpacket = 1'b0; in_data = 1'b0; # (CLK_PRD * 3); end # (CLK_PRD * 20); $display("DONE"); $stop; end /////////////////////////////////////////////////////////////////// // DUT /////////////////////////////////////////////////////////////////// altera_avalon_sc_fifo# ( .SYMBOLS_PER_BEAT (8 ), .BITS_PER_SYMBOL (8 ), .FIFO_DEPTH (1024 ), .CHANNEL_WIDTH (0 ), .ERROR_WIDTH (1 ), .USE_PACKETS (1 ), .USE_FILL_LEVEL (1 ), .USE_STORE_FORWARD (1 ), .USE_ALMOST_FULL_IF (0 ), .USE_ALMOST_EMPTY_IF (0 ), .EMPTY_LATENCY (3 ), .USE_MEMORY_BLOCKS (1 ) ) dut ( .clk (i_clk ), .reset (i_rst ), .in_data (in_data ), .in_valid (in_valid ), .in_startofpacket (in_startofpacket ), .in_endofpacket (in_endofpacket ), .in_empty (in_empty ), .in_error (in_error ), .in_channel (in_channel ), .in_ready (in_ready ), .out_data (out_data ), .out_valid (out_valid ), .out_startofpacket (out_startofpacket ), .out_endofpacket (out_endofpacket ), .out_empty (out_empty ), .out_error (out_error ), .out_channel (out_channel ), .out_ready (out_ready ), .csr_address (csr_address ), .csr_write (csr_write ), .csr_read (csr_read ), .csr_writedata (csr_writedata ), .csr_readdata (csr_readdata ), .almost_full_data (almost_full_data ), .almost_empty_data (almost_empty_data )); endmodule
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