FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6382 Discussions

SDI Megacore refclk_rate

Altera_Forum
Honored Contributor II
972 Views

In the v11 SDI userguide it describes the new signal refclk_rate with the following: 

 

refclk_rate : Input : Set input 0 for a 148.35-MHz RX serial reference clock and input 1 

for 148.35-MHz RX serial reference clock. 

 

Ok, so what do I set it to for 148.5MHZ ref clock?:confused: 

 

Cheers, 

Simon
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
294 Views

i filed an SR on this: 

 

Below statement is the corrected one. 

Set input 0 for a 148.35-MHz RX serial reference clock and input 1 for 148.5-MHz RX serial reference clock.
0 Kudos
Altera_Forum
Honored Contributor II
294 Views

Thanks! That seems to work.

0 Kudos
Reply