I am attempting to connect the Altera PCIE core to a Denali PCIE Model for simulation purposes. I looked through the Stratix Hard IP for PCIE User Guide but could not find any data on how to communicate electrical idles/receiver detection to the Altera PCIE core.
Also the generated PCIE Core ports to not include differential pairs. It appears that Denali uses the differential pairs to distinguish Receiver Detection.
i.e.
TX/TX_= 0,1 or 1,0 means active
TX/TX_ = Z/Z electrical idle
TX/TX_ = 0/0 receiver
How does the Altera PCIE core map to the table above?
Can we generate a PCIE Core with differential pairs?
