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5954 Discussions

SGDMA descriptor problem?

Honored Contributor II



I have been trying to get do a memory to memory transfer(from custom memory mapped component to ddr2 ram) using sgdma in qsys. Im running uclinux and so cannot use the altera HAL driver. 



This is my setup: 

Both the read and write masters of descriptor block connect to onchip ram to store my descriptors. 

CSR slave connected to niosII data master. 

Read master connected to my custom component slave. 

Write masters connected to ddr2. 


I think i have the setup correct but might be having troubles with setting up the descriptor. 


I write the address of my descriptor in the next_descriptor_pointer of the control/status register. 


The descriptor has the source address of my custom component and destination address of ddr2(using kmalloc in linux kernel) and the next_desc_ptr points to this same descriptor again(i think this is where im doing it wrong). Is it ok to use 1 descriptor or do i need to have atleast two and point to the second desc from the first. 


Help appreciated!
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3 Replies
Honored Contributor II

flush the data cache

Honored Contributor II

Might be worth looking at the HAL driver to figure out what it does. Unless it has changed the driver sets up the the descriptor structure and one of the last steps is it performs a flush by address to ensure that the structure is written out to memory. Also make sure that the descriptor in memory is aligned to the wide of the descriptor read/write masters. I think by default the descriptor masters are 256-bit so they expect to read/write a descriptor in a single transaction, I think you can configure them to be 32-bit but I'm not 100% sure you if 32-bit alignment of the descriptor in memory will work (use 256-bit to play it safe in that case).

Honored Contributor II

Have you worked it out? And I am confusing about this ,too. Can you help me? Thanks very much!