SOPC read latency question

Altera_Forum · ‎06-06-2009

Hi, I have a novice question about the SOPC builder.

I made a simple component in the Component Editor which is a just a RAM. The RAM's VHDL was created with the Mega-Wizard Plug-in manager. It has 32-bit wide data, 8-bit address, registered read and write, and both read and write enables. I connected it up as an Avalon Slave choosing write latency of 0 and read latency of 1. I saw the cute little timing diagrams that the Component Editor displays and they looked as I expected. The component is connected directly to the data master of a Nios II/s with no bridge. It uses the same clock as the processor.

I find that I can read and write to the memory locations corresponding to my component, using IORD and IOWR in a C program. Good news! However, there is something strange. If I write four different numbers to four different locations, and then read them back out, I get the same four numbers out but in a **different order**. Is there a pipeline so that when I read or write I am really reading or writing a previous number? Is the pipeline on both read and write or only one of them? Does this have to do with the latency setting I chose when I made the component, or is it a feature of the processor? Or of the Avalon fabric? Where can I read about this and what is the safe way to handle it in software? Thanks!

Altera_Forum · ‎06-08-2009

Hi,

When you set read latency in the Component Editor to 1, you are indeed creating a pipelined system where the next read can be issued before the data from the first read is returned. This is only an option for read cycles; write cycles cannot be pipelined.

You might try looking at the sample waveforms generated by the MegaWizard Plug-in manager (Documentation Button -> Generate Sample Waveforms) and comparing them to the Component Editor settings. If you are registering the output of the memory then you will have to wait an extra cycle.

I suggest reading http://www.altera.com/literature/manual/mnl_avalon_spec.pdf for the details on the timing options available when interfacing with an Avalon bus.

This is a hardware issue and should be dealt with in hardware. There may be workarounds such as issuing double reads to the same address and discarding the first one - but these are unreliable and unnecessary, since we have full control over the hardware timing.

Altera_Forum · ‎06-09-2009

Thanks very much for your reply. I have read the Avalon spec and I realize now that I used incorrect language in my question. In fact, I set up the slave with zero latency (no pipeline), zero write wait states and one read wait state. I don't know why there should be a read pipeline delay in this case. I have played around a bit more with the C code and it definitely does behave like the read has a pipeline delay of one. I have done an rtl simulation of the peripheral and it behaves as I expect. I do have the output registered and so I understand why I need the read wait state. But I don't understand where the pipeline delay is coming from.

Altera_Forum · ‎06-09-2009

If you are a Xilinx guy, remember NIOS is little endian and so should your components be.

Post your:

1 - C code

2 - VHDL source file

3 - TCL file generated by component wizard.

Then will have it explained and fixed in a jiffy.

Jake

Altera_Forum · ‎06-09-2009

Here are the files. The component is connected directly to the data master of a Nios II/s with no bridge. The included C code does read correctly the written data, but it has to fill the pipeline first. What I don't get is why there is a pipeline. Thanks!!

Altera_Forum · ‎06-10-2009

Okay try the attached version instead.

I changed your read wait states on the component to 0 and your read latency to 2 (to match the registered input and output of the RAM block).

Jake

Altera_Forum · ‎06-15-2009

Yes, that does it. First time I didn't read the Avalon spec, then I read it, then I read it *carefully*. Now I get it!

Thanks