SPI Master Ip in Quartus prime lite

[infinite]

Please give me an example of SPI master IP interfacing with max10 FPGA in Quartus prime lite 22.1. I wanted to read the data from slave device.

And how to verify this data?

[ShengN_Intel]

Hi,

You may checkout this example design https://www.intel.com/content/www/us/en/design-example/715042/max-10-spi-slave-to-avalon-master-bridge-for-max10-dev-kit.html and modify a bit the platform designer system so that the spi master is connected to slave device like screenshot attached below.

To verify the read data, you may try out this Example Test Code using alt_avalon_spi_command() https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/example-test-code.html. Expected result like the screenshot attached below. Or may be can also access the register map https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/register-map-75450.html

Thanks,

Best Regards,

Sheng