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Altera_Forum
Honored Contributor I
1,150 Views

SRAM -> Frame Reader -> 2D FIR Filter -> SRAM

Hi, 

 

I'm currently working on a small project, were I want to transfer pictures from a PC via RS-232 to a EP2S180 Board. This pictures are stored in the SRAM. (works well) 

After that, I would like to do a convolution filtering on that picture. The result should also be stored in the sram. At the end, the filtered image is send back to the PC-Software via RS-232. (already works) 

 

My abroach to do the filtering would be to use a frame-reader, 2D-FIR-Filter and a SG-DMA like shown in the attached picture. 

 

First of all, could somebody tell me, if this is the right way, or if it is even possible in this way? 

 

Thank you in advance
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2 Replies
Altera_Forum
Honored Contributor I
50 Views

I tryed to get the filter running, but it does not really work. 

I configured the frame reader, the FIR-Filter and the SG-DMA as you can see in the attached pictures. 

 

 

In my software I do the following: 

 

1. Init. and start the sg-dma 

In my main function: // Open a SG-DMA for ST-->MM alt_sgdma_dev* receive_DMA = alt_avalon_sgdma_open("/dev/stream_to_memory"); alt_sgdma_descriptor *receive_descriptors, *receive_descriptors_copy; alt_u32 return_code; if(receive_DMA == NULL) { printf("Could not open the receive SG-DMA\n"); setState(STATE_SEND_TIME, 0); } return_code = descriptor_allocation(&receive_descriptors, &receive_descriptors_copy, 1); alt_avalon_sgdma_construct_stream_to_mem_desc(&receive_descriptors, // descriptor &receive_descriptors, // next descriptor FILT_IMAGE, // write buffer location (0x140000) (alt_u16)(iImageSize), // length of the buffer (4096 in my test -> 64x64 image) 0); // writes are not to a fixed location alt_avalon_sgdma_register_callback(receive_DMA, &receive_callback_function, (ALTERA_AVALON_SGDMA_CONTROL_IE_GLOBAL_MSK |ALTERA_AVALON_SGDMA_CONTROL_IE_CHAIN_COMPLETED_MSK), NULL); The descriptor allocation: alt_u32 descriptor_allocation(alt_sgdma_descriptor ** receive_descriptors, alt_sgdma_descriptor ** receive_descriptors_copy, alt_u32 number_of_buffers) { void * temp_ptr_1; temp_ptr_1 = malloc((number_of_buffers + 2) * ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE); if(temp_ptr_1 == NULL) { printf("Failed to allocate memory for the receive descriptors\n"); return 1; } *receive_descriptors_copy = (alt_sgdma_descriptor *)temp_ptr_1; while((((alt_u32)temp_ptr_1) % ALTERA_AVALON_SGDMA_DESCRIPTOR_SIZE) != 0) { temp_ptr_1++; // slide the pointer until 32 byte boundary is found } *receive_descriptors = (alt_sgdma_descriptor *)temp_ptr_1; // Clear out the null descriptor owned by hardware bit. receive_descriptors->control = 0; return 0; // no failures in allocation } 2. Init. and start the frame reader 

 

static const int pb0_base_addressoffset = 4; static const int pb0_words_addressoffset = 5; static const int pb0_samples_addressoffset = 6; static const int pb0_width_addressoffset = 8; static const int pb0_height_addressoffset = 9; static const int pb0_interlaced_addressoffset = 10; static const int packet_bank_addressoffset = 3; //register isr alt_ic_isr_register(ALT_VIP_VFR_0_IRQ_INTERRUPT_CONTROLLER_ID, irq, FR_ISR, 0, 0); //config FR_do_write(pb0_base_addressoffset, base_address); //address of my image in the sram (0x100000) FR_do_write(pb0_words_addressoffset, words); // words = (64x64) / (32/8) --> 1024 FR_do_write(pb0_samples_addressoffset, samples); // samples = 4096 FR_do_write(pb0_width_addressoffset, width); // width = 64 FR_do_write(pb0_height_addressoffset, height); // height = 64 FR_do_write(pb0_interlaced_addressoffset, interlaced);//interlaced = 3 --> progressiv?! FR_do_write(packet_bank_addressoffset, 0); //start FR_enable_interrupt(INTERRUPT); control = control | 1; FR_do_write(GO, control); void FR_do_write(int offset, int value) { IOWR(ALT_VIP_VFR_0_BASE, offset, value); } The frame reader interrupt fires, but the sg-dma interrupt does not. 

And there is nothing written to my target memory. 

Does anybody see, what I am doing wrong here?
Altera_Forum
Honored Contributor I
50 Views

Ahh, and I get a lot of warnings related to the frame reader during the sopc generation process. But I dont have a clue why...  

 

Warning: Warning (10238): Verilog Module Declaration warning at alt_vipvfr110_prc_read_master.v(47): ignored anonymous port(s) indicated by duplicate or dangling comma(s) in the port list for module "alt_vipvfr110_prc_read_master" Warning: Warning (10236): Verilog HDL Implicit Net warning at alt_vipvfr110_prc.v(142): created implicit net for "master_clock" Warning: Warning (10236): Verilog HDL Implicit Net warning at alt_vipvfr110_prc.v(143): created implicit net for "master_reset" Warning: Warning (10445): VHDL Subtype or Type Declaration warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(178): subtype or type has null range Warning: Warning (10445): VHDL Subtype or Type Declaration warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(181): subtype or type has null range Warning: Warning (10445): VHDL Subtype or Type Declaration warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(261): subtype or type has null range Warning: Warning (10445): VHDL Subtype or Type Declaration warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(262): subtype or type has null range Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(178): object "wdata_fifo_wrusedw" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(179): object "wdata_fifo_full" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(180): object "wdata_fifo_almost_full" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(182): object "wdata_fifo_empty" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(183): object "wdata_fifo_almost_empty" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(184): object "wdata_fifo_wrreq" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(185): object "wdata_fifo_data" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(186): object "wdata_fifo_rdreq" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(187): object "wdata_fifo_q" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(189): object "wdata_fifo_empty_next" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(193): object "rdata_fifo_full" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(194): object "rdata_fifo_almost_full" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(195): object "rdata_fifo_rdusedw" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(197): object "rdata_fifo_almost_empty" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(212): object "cmd_fifo_wrusedw" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(214): object "cmd_fifo_almost_full" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(215): object "cmd_fifo_rdusedw" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(217): object "cmd_fifo_almost_empty" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(229): object "writing" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(229): object "reading" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(239): object "wdata_en" assigned a value but never read Warning: Warning (10541): VHDL Signal Declaration warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(260): used implicit default value for signal "byte_enable_next" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. Warning: Warning (10296): VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(424): ignored assignment of value to null range Warning: Warning (10296): VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(425): ignored assignment of value to null range Warning: Warning (10296): VHDL warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(437): ignored assignment of value to null range Warning: Warning (10631): VHDL Process Statement warning at alt_vipvfr110_common_avalon_mm_bursting_master_fifo.vhd(641): inferring latch(es) for signal or variable "byte_enable", which holds its previous value in one or more paths through the process Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_general_fifo.vhd(230): object "ram_fifo_empty" assigned a value but never read Warning: Warning (10036): Verilog HDL or VHDL warning at alt_vipvfr110_common_ram_fifo.vhd(129): object "port_a_q" assigned a value but never read Warning: Warning (10240): Verilog HDL Always Construct warning at alt_vipvfr110_common_avalon_mm_slave.v(45): inferring latch(es) for variable "interrupt_register", which holds its previous value in one or more paths through the always construct Warning: Warning (10230): Verilog HDL assignment warning at alt_vipvfr110_common_avalon_mm_slave.v(72): truncated value with size 35 to match size of target (32) Warning: Warning (10240): Verilog HDL Always Construct warning at alt_vipvfr110_common_avalon_mm_slave.v(45): inferring latch(es) for variable "interrupt_register", which holds its previous value in one or more paths through the always construct Warning: Warning (10230): Verilog HDL assignment warning at alt_vipvfr110_common_avalon_mm_slave.v(72): truncated value with size 49 to match size of target (32) Warning: Warning (10240): Verilog HDL Always Construct warning at alt_vipvfr110_vfr_control_packet_encoder.v(62): inferring latch(es) for variable "control_data", which holds its previous value in one or more paths through the always construct Warning: Warning (10230): Verilog HDL assignment warning at alt_vipvfr110_vfr_control_packet_encoder.v(82): truncated value with size 32 to match size of target (4)
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