FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

Inphase (I) and Quadrature (Q) components of signals

Arria V PCIe Hard IP sees stale data

rapidio Gen1 and rapidio Gen2

Multiple (concatenated) DDR3 interface

Interfacing with Altera-MM Salve of UniPHY DDR2 controller

Simple question about SDI IP

CAS Latency on Cyclone V DDR2 Hard Memory Controller

"auto-refresh" selection of hpcii is enbled,but the local_refresh_req is set 0 ?

a question about the precharge operation of hpc ii?

Triple SDI RX - Clocked Video Input Interface

SD-SDI 8bit

Error while generating DDR2 IP core for CycloneIV in Quartus13.1

QDRII+ UniPHY - Change afi_half_clk phase

Using CIC Decimation Filter with Multi-channel Support

How can i use negedge of the clock in dspbuilder?

Featured Content

where to find testbench with Scalable Switch Intel® FPGA IP for PCI Express?

Differences between SSGDMA and GTS MCDMA for Agilex 5

Over 4GB PCIe BAR Size Issue

Re: How to implement PCIE hard IP for Cyclone IV GX

Re: PCIe 6.0