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Hi All,
How many lanes are supported by Intel Serial Lite IP?
Thank you!
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Hi,
As I understand it, you have some inquiries related to the SerialLite IP for FPGA. For your information, you may explore into the Serial Lite III IP and refer to the following user guide for further details:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_slite3_streaming.pdf
Regarding your inquiry on the maximum lanes can be supported, as I understand it, this would be dependent on the device that you are using. You may refer to the "Performance and Resource Utilization" section in the uesr guide for further details.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
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Hi,
As I understand it, you have some inquiries related to the SerialLite IP for FPGA. For your information, you may explore into the Serial Lite III IP and refer to the following user guide for further details:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_slite3_streaming.pdf
Regarding your inquiry on the maximum lanes can be supported, as I understand it, this would be dependent on the device that you are using. You may refer to the "Performance and Resource Utilization" section in the uesr guide for further details.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
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Hi,
I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
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