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SerialLite II channel_up drops to '0' on burst of data

Altera_Forum
Honored Contributor II
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Hi, 

 

I’m trying to bring-up a Transceivers link using the SerialLite II protocol between Stratix 4 (EP4SGX230KF40C2) & Arria 2 GX (EP2AGX260EF29I5) FPGAs. 

The FPGAs are placed on different PCBS: 

 

  1. The Startix 4 is on a DE4 evaluation board. 

  2. The boards are connected with a flat cable (on the DE4 side it is connected to the HSMB connector – J21 – on the upper third – pins 1,3 & 2,4). 

 

I followed the instructions on the user guide in my design: 

 

  1. Generated the SerialLite II core and also a basic Transceivers Reconfig block, and connected them. 

  2. I used the following configuration for the SerialLite II core: 

  3. Data rate: 1000Mbps. 

  4. Transfer size: 2 columns. 

  5. Reference frequency: 100MHz. 

  6. Bidirectional, 1 lane to each direction. 

  7. I enabled frequency offset tolerance, though I’m not sure it is needed. I set it for 100ns. 

  8. I didn’t change the default configuration for the Transceiver. 

  9. Link Layer: Streaming. 

  10. On startup, I provide the following initialization: 

  11. The SerialLite II core’s gxb_powerdown & mreset_n are active for 4 mili-seconds. 

  12. After 4 ms, the reset & powerdown are released, the SerialLite trains with the opposite side. 

  13. The logic using the SerialLite core waits for a consistent “channel_up” HIGH indication (I saw that the core outputs HIGH when it is on reset, so after the reset is released the logic 

 

using the SerialLite wait a short period for the channel_up to be LOW and then waits for it to become consistently HIGH, meaning that the training is over and the link is up). 

 

  1. The calibration clock & reconfig clock for the transceiver are fed from a 50Mhz clock. This clock is also used to control the SerialLite II initialization discussed on 3. 

  2. Of course – when synthesizing, I ran the TCL script for timing constraints, generated by the megawizard. 

 

This design was simulated and seems to be working well on simulation – the channel_up indication is becoming high on both sides and each side transmits and receives the correct data from the opposite. 

 

But when trying to bring-up up on the PCBs, I encounter a problem. The training seems to be running correctly and channel_up becomes constantly HIGH, but as soon as I start transmitting a large amount of data from the Arria to the Stratix - the channel_up indication of the Arria drops to be LOW for about ~5 micro-seconds. After, It returns to be HIGH. This causes invalid behavior of my upper layer system using the SerialLite. 

Can you help me understand why is it happening ? How can I solve it ? What has been done wrongly ? 

 

I compiled & generated the cores with Quartus II 64-bit version 11.0 SP1. 

 

Thanks.
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