FPGA Intellectual Property

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FPGA Intellectual Property

Discussions

Help with DDR2 SDRAM DIMM with UniPHY on Stratix III eval board

test pattern generator (VIP)

Reed Solomon IPcore 13.0 problem

Altera Compact flash IP Core Performance

Serial RapidIO Mesh Network?

DDR2 half-rate works, not full-rate

Output Latency for Integer Arithmetic Megacore at Cyclon Family

sopc_buider_IP Core

Using Serial RapidIO?

Problems with UniPHY IP not accepting commands on Cadence

UDP Offload example

Need help with DE2 Audio Codec

Stratix V PCIE hardcore not detected in bios with Intel chipset C600

XAUI core simulation for Cyclone V

Getting started with a 3 port ethernet design

Featured Content

Tone Mapping Operator IP Malfunctioning

dynamic configuration issue of fpll from arria 10

Unable to simulate DDR3 controller

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)

Re: ALTPLL dynamic phase shift: c0/c1 shift in opposite directions; c2 does not shift (Stratix IV)