SerialLite IP on Xilinx device

[Altera_Forum]

I am wondering if it is "possible" to implement the SerialLite IP on a Xilinx device? 

 I know that theoretically one can implement the IP from scratch on any device, but that would probably be too much of an effort. I want to know to what degree one can use the generated files (and I don't know exactly what files those are!) for the IP and modify them to fit on a Xilinx device.

[Altera_Forum]

To my opinion this will not work. Sure pure digital logig written in HDL can easily be ported. But a high speed serial protocol? I am pretty sure that this IP makes use of hard wired logic cells on the chip and therefore it will not be portable to a Xilinx device. It isn't either for an Altera Cyclone device.

[Altera_Forum]

--- Quote Start ---  I am wondering if it is "possible" to implement the SerialLite IP on a Xilinx device?   I know that theoretically one can implement the IP from scratch on any device, but that would probably be too much of an effort. I want to know to what degree one can use the generated files (and I don't know exactly what files those are!) for the IP and modify them to fit on a Xilinx device.  --- Quote End ---     No, the megacore IPs are encrypted and their complete code is not available for users to edit.

[Altera_Forum]

Ok, thanks. 

 I have an idea that one can instead use the Aurora IP from Xilinx and modify it to support SerialLite. The two protocols are fairly similar, and the Aurora IP is completely editable VHDL. What do you think about that?

[Altera_Forum]

I don't know about Aurora IP, but if (a) it is a completely editable entity and (b) doesn't use any Xilinx-specific constructs, then it is as good as any generic HDL design. It can then be used with any synthesis tool.